[Suzaku:00768] Re: RAMサイズとコントロール回路について

Shinji Ito email@hidden
2007年 1月 29日 (月) 18:06:28 JST


$B=i$a$^$7$F!"0KF#$H?=$7$^$9!#(B

EDK$BIUB0$N(Bbram_if_cntr$B$O!"@\B3$9$k%P%9$HF1$8%S%C%HI}$G$J$$$H(B
$B$$$1$^$;$s!#(B
(PLB$B$N>l9g$O(B64bit$B!"(BOPB$B$N>l9g$O(B32bit)

$B99$K(BCPU$B$+$i%=%U%H%&%'%"$G%"%/%;%9$5$l$k;v$r9MN8$7$F!"%P%9I}(B
$B$KBP$7$F%P%$%HC10L$K%i%$%H$G$-$kI,MW$,$"$j$^$9!#(B

VirtexIIPro$B$N(BBRAM$B$O(B1$B8DEv$j(B2KB$B%P%$%H$G!"%S%C%HI}$O(B32bit$B$^$G(B
$email@hidden$G$-$^$9$,!"%i%$%H;~$N%P%$%H%$%M!<%V%k$,$"$j$^$;$s!#(B

$B$=$N$?$a!"(BPLB$B%P%9$K@\B3$9$k>l9g$O(B8$B8D(B(16KB)$BC10L$G$7$+@\B3$G(B
$B$-$^$;$s!#(B
$BF1MM$K(BOPB$B$N>l9g$O(B4$B8D(B(8KB)$BC10L$K$J$j$^$9!#(B

$B$3$N@)8B$O(BCPU$B$^$?$O$=$NB>$N%P%9%^%9%?$+$i(B64$B%S%C%H%"%/%;%9(B
$B$5$l$k$+$I$&$+$H$O4X78$J$/0lN'$KE,MQ$5$l$F$7$^$$$^$9!#(B

Virtex4$B$N(BBRAM$B$J$i(B8$B%S%C%HC10L$K%i%$%H;~$N%P%$%H%$%M!<%V%k$,(B
$email@hidden$G$-$k$N$G!"(BPLB$B$K@\B3$9$k>l9g$G$b(B2$B8D(B(4KB)$BC10L$G@\B3$G(B
$B$-$k$N$G$9$,!D(B

$B>e5-$N$h$&$JM}M3$G!"(BEDK$BE:IU$N(Bplb_bram_if_cntlr$B$r;HMQ$9$k(B
$B>l9g$O!"%5%$%:$O(B16KB$B!A$H$J$j$^$9!#(B

==============================
$B0KF#(B $B?5<#(B
email@hidden
==============================

^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
2007/01/29 17:17:53
[[Suzaku:00766] Re: RAM$B%5%$%:$H%3%s%H%m!<%k2sO)$K$D$$$F(B]
From: Yasushi SHOJI
To: SUZAKU general discussion list <email@hidden>
CC: --

> At Mon, 29 Jan 2007 14:25:10 +0900,
> <email@hidden> wrote:
> > 
> > > > $B!!(BMemoryBlock$B$H(BMemory$B%3%s%H%m!<%i$r(BOPB$B%P%9$K@\B3$7$F$$$^$9!#(B
> > > > $B!!(BRAM$B%5%$%:$H$7$F$O!"#2(BKB$B#y(Bte$B$G==J,$G$9$,!"(B
> > > > $B!!(BSUZAKU-V$B$K@\B3$5$l$F$$$k(BViterx$B-6$N;EMM$+$i(B32-bit data$B!"(B
> > > > $B!!#8(BKB$B!!(BRAM$B$rA*Br$9$kM=Dj$G$9!#(B
> > > > $B!!$h$C$F%a%b%j%^%C%W$H$7$F$O!"(B0000-1FFF$BNN0h$r3NJ]$7$F$$$^$9$,!"(B
> > > > $B!!(B64bit$B%G!<%?$H$7$FG'<1$5$l$k$h$&$G!"0J2<$N%5%$%:%(%i!<$,H/@8$7$^$9!#(B
> > > > 
> > > > $B!!$b$A$m$s!"(B16K$B$KNN0h$rA}$d$9$3$H$G%(%i!<$O2sHr$G$-$^$9$,!"(BRAM$B$N#1#6(Bbit,32bit$B%"%/%;%9(B
> > > > $B!!$NA*BrJ}K!$,$o$+$j$^$;$s$N$G!"65$($F2<$5$$!#(B
> > > > 
> > > > $B!!$h$m$7$/$*4j$$$7$^$9!#(B
> > > > 
> > > 
> > > $B2<5-%(%i!<$O!"(B"plb_bram_if_cntlr"$B$N%(%i!<$N$h$&$G$9!#(B
> > > 
> > > 16,32bit$B%"%/%;%9$r$9$k>l9g$O(Bopb_bram_if_cntlr$B$r;H$C$F$/$@$5$$!#(B
> > > 
> > 
> > $B!!:#2s$N%7%9%F%`$O9bB.$K%"%/%;%9$5$;$k$?$a$K!"(BPLB$B%P%9A0Ds$email@hidden$7$F$$$^$9!#(B
> 
> $B>e5-$G(B OPB$B$H$"$k$N$G!"(BOPB$B$K@\B3$7$F$$$k$N$+$H;W$$$^$7$?!#(B
> 
> > $B!!(BPLB$B%P%9$K@\B3$9$k>l9g$O!"(B64$B%S%C%H%"%/%;%9$9$k$7$+$J$$$H$$$&$3$H$G$7$g$&$+!)(B
> 
> CPU$B$+$i$N%"%/%;%9$O(B64bit$B0J30$G$b2DG=$G$9!#2<5-(BURL$B$N%I%-%e%a%s%H$NKAF,(B
> $B$K$b!V(BThis controller supports the PLB V3.4 byte enable
> architecture. Any access size up to the width of the PLB data bus is
> permitted.$B!W$H$"$j$^$9!#(B
> 
> > $B!!$@$H$9$k$H:email@hidden$9$kI,MW$,$"$j!"%9%1%8%e!<%k$K1F6A$rM?$($^$9!#(B
> > $B!!;EMM=q$rFI$_<h$l$J$+$C$?2f!9$KLdBj$,$"$k$N$G$9$,!"(B
> > $B!!(BPLB$B!!(BBlock$B!!(BRAM$B!!(BIf Control (V1.00b) $B$K$O(B32bit $B$G$bLdBj$J$$$h$&$K8+<u$1$i$l$k(B
> > $B!!$N$G$9$,!"FI$_0c$$$G$7$g$&$+!)(B
> 
> Xilinx$B$K$"$k(B PLB Block RAM Interface Controller (v1.00b)$B$r;2>H$7$F$$$k(B
> $B$N$G$9$,!""-(B
> 
>     http://www.xilinx.com/bvdocs/ipcenter/data_sheet/plb_bram_if_cntlr.pdf
> 
> table 4: Supported BRAM memory sizes for Virtex-II and Virtex-II Pro
> 
> Host Bus Size    Supported Memory Sizes (Bytes)
>     (bits)
>       32           8KB, 16KB, 32KB, 64KB
>       64          16KB, 32KB, 64KB, 128KB
> 
> $B$H$"$j!"$?$7$+$K(B 32bit$B$H(B 64bit$B$,5-:\$5$l$F$$$^$9!#$?$@$7!"(BPLB$B$N%G!<%?(B
> $B%P%9$NI}$OF1$8%I%-%e%a%s%H$N!V(BTable 2: PLB BRAM Interface Controller
> Parameters$B!W$K$"$k$h$&$K!"(B64bit$B8GDj$G$9!#(B
> 
> table 4$B$N(B 32bit$B$NI=5-$O!"(Bplb$B$G$O$J$/!"$?$H$($P(B 32bit$BI}$N(B fifo$B$J$I$K@\(B
> $BB3$9$k>l9g$G$O$J$$$G$7$g$&$+!)(B
> 
> CPU$B$+$i$N%"%/%;%9I}$H!"(BPLB$B$H(Bbram$B%3%s%H%m!<%i$N@\B3I}$K0c$$$,$"$k$H$$$&(B
> $B$3$H$G$O$J$$$G$7$g$&$+!)(B
> -- 
>         yashi
> 





suzaku メーリングリストの案内