[Suzaku:00769] Re: RAMサイズとコントロール回路について

$B0KF#MM!"(J $B%7%g%&%8MM(J

$BDUB<$G$9!#(J

$B0J2<CzG+$email@hidden@$"$j$,$H$&$4$6$$$^$7$?!#(J
$B$h$/M}2r$G$-$^$7$?!#(J

64bit$B$KJQ99$7$FBP1~$7$^$9!#(J



> -----Original Message-----
> From: email@hidden 
> [mailto:email@hidden] On Behalf Of 
> Shinji Ito
> Sent: Monday, January 29, 2007 6:06 PM
> To: SUZAKU general discussion list
> Subject: [Suzaku:00768] Re: RAM$B%5%$%:$H%3%s%H%m!<%k2sO)$K$D$$$F(J
> 
> $B=i$a$^$7$F!"0KF#$H?=$7$^$9!#(J
> 
> EDK$BIUB0$N(Jbram_if_cntr$B$O!"@\B3$9$k%P%9$HF1$8%S%C%HI}$G$J$$$H(J
> $B$$$1$^$;$s!#(J
> (PLB$B$N>l9g$O(J64bit$B!"(JOPB$B$N>l9g$O(J32bit)
> 
> $B99$K(JCPU$B$+$i%=%U%H%&%'%"$G%"%/%;%9$5$l$k;v$r9MN8$7$F!"%P%9I}(J
> $B$KBP$7$F%P%$%HC10L$K%i%$%H$G$-$kI,MW$,$"$j$^$9!#(J
> 
> VirtexIIPro$B$N(JBRAM$B$O(J1$B8DEv$j(J2KB$B%P%$%H$G!"%S%C%HI}$O(J32bit$B$^$G(J
> $email@hidden$G$-$^$9$,!"%i%$%H;~$N%P%$%H%$%M!<%V%k$,$"$j$^$;$s!#(J
> 
> $B$=$N$?$a!"(JPLB$B%P%9$K@\B3$9$k>l9g$O(J8$B8D(J(16KB)$BC10L$G$7$+@\B3$G(J
> $B$-$^$;$s!#(J
> $BF1MM$K(JOPB$B$N>l9g$O(J4$B8D(J(8KB)$BC10L$K$J$j$^$9!#(J
> 
> $B$3$N@)8B$O(JCPU$B$^$?$O$=$NB>$N%P%9%^%9%?$+$i(J64$B%S%C%H%"%/%;%9(J
> $B$5$l$k$+$I$&$+$H$O4X78$J$/0lN'$KE,MQ$5$l$F$7$^$$$^$9!#(J
> 
> Virtex4$B$N(JBRAM$B$J$i(J8$B%S%C%HC10L$K%i%$%H;~$N%P%$%H%$%M!<%V%k$,(J
> $email@hidden$G$-$k$N$G!"(JPLB$B$K@\B3$9$k>l9g$G$b(J2$B8D(J(4KB)$BC10L$G@\B3$G(J
> $B$-$k$N$G$9$,!D(J
> 
> $B>e5-$N$h$&$JM}M3$G!"(JEDK$BE:IU$N(Jplb_bram_if_cntlr$B$r;HMQ$9$k(J
> $B>l9g$O!"%5%$%:$O(J16KB$B!A$H$J$j$^$9!#(J
> 
> ==============================
> $B0KF#(J $B?5<#(J
> email@hidden
> ==============================
> 
> ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
> 2007/01/29 17:17:53
> [[Suzaku:00766] Re: RAM$B%5%$%:$H%3%s%H%m!<%k2sO)$K$D$$$F(J]
> From: Yasushi SHOJI
> To: SUZAKU general discussion list <email@hidden>
> CC: --
> 
> > At Mon, 29 Jan 2007 14:25:10 +0900,
> > <email@hidden> wrote:
> > > 
> > > > > $B!!(JMemoryBlock$B$H(JMemory$B%3%s%H%m!<%i$r(JOPB$B%P%9$K@\B3$7$F$$$^$9!#(J
> > > > > $B!!(JRAM$B%5%$%:$H$7$F$O!"#2(JKB$B#y(Jte$B$G==J,$G$9$,!"(J
> > > > > $B!!(JSUZAKU-V$B$K@\B3$5$l$F$$$k(JViterx$B-6$N;EMM$+$i(J32-bit data$B!"(J
> > > > > $B!!#8(JKB$B!!(JRAM$B$rA*Br$9$kM=Dj$G$9!#(J
> > > > > $B!!$h$C$F%a%b%j%^%C%W$H$7$F$O!"(J0000-1FFF$BNN0h$r3NJ]$7$F$$$^$9$,!"(J
> > > > > $B!!(J64bit$B%G!<%?$H$7$FG'<1$5$l$k$h$&$G!"0J2<$N%5%$%:%(%i!<$,H/@8$7$^$9!#(J
> > > > > 
> > > > > $B!!$b$A$m$s!"(J16K$B$KNN0h$rA}$d$9$3$H$G%(%i!<$O2sHr$G$-$^$9$,!"(JRAM$B$N#1#6(Jbit,32bit$B%"%/%;%9(J
> > > > > $B!!$NA*BrJ}K!$,$o$+$j$^$;$s$N$G!"65$($F2<$5$$!#(J
> > > > > 
> > > > > $B!!$h$m$7$/$*4j$$$7$^$9!#(J
> > > > > 
> > > > 
> > > > $B2<5-%(%i!<$O!"(J"plb_bram_if_cntlr"$B$N%(%i!<$N$h$&$G$9!#(J
> > > > 
> > > > 16,32bit$B%"%/%;%9$r$9$k>l9g$O(Jopb_bram_if_cntlr$B$r;H$C$F$/$@$5$$!#(J
> > > > 
> > > 
> > > $B!!:#2s$N%7%9%F%`$O9bB.$K%"%/%;%9$5$;$k$?$a$K!"(JPLB$B%P%9A0Ds$email@hidden$7$F$$$^$9!#(J
> > 
> > $B>e5-$G(J OPB$B$H$"$k$N$G!"(JOPB$B$K@\B3$7$F$$$k$N$+$H;W$$$^$7$?!#(J
> > 
> > > $B!!(JPLB$B%P%9$K@\B3$9$k>l9g$O!"(J64$B%S%C%H%"%/%;%9$9$k$7$+$J$$$H$$$&$3$H$G$7$g$&$+!)(J
> > 
> > CPU$B$+$i$N%"%/%;%9$O(J64bit$B0J30$G$b2DG=$G$9!#2<5-(JURL$B$N%I%-%e%a%s%H$NKAF,(J
> > $B$K$b!V(JThis controller supports the PLB V3.4 byte enable
> > architecture. Any access size up to the width of the PLB data bus is
> > permitted.$B!W$H$"$j$^$9!#(J
> > 
> > > $B!!$@$H$9$k$H:email@hidden$9$kI,MW$,$"$j!"%9%1%8%e!<%k$K1F6A$rM?$($^$9!#(J
> > > $B!!;EMM=q$rFI$_<h$l$J$+$C$?2f!9$KLdBj$,$"$k$N$G$9$,!"(J
> > > $B!!(JPLB$B!!(JBlock$B!!(JRAM$B!!(JIf Control (V1.00b) $B$K$O(J32bit $B$G$bLdBj$J$$$h$&$K8+<u$1$i$l$k(J
> > > $B!!$N$G$9$,!"FI$_0c$$$G$7$g$&$+!)(J
> > 
> > Xilinx$B$K$"$k(J PLB Block RAM Interface Controller (v1.00b)$B$r;2>H$7$F$$$k(J
> > $B$N$G$9$,!""-(J
> > 
> >     
> http://www.xilinx.com/bvdocs/ipcenter/data_sheet/plb_bram_if_cntlr.pdf
> > 
> > table 4: Supported BRAM memory sizes for Virtex-II and Virtex-II Pro
> > 
> > Host Bus Size    Supported Memory Sizes (Bytes)
> >     (bits)
> >       32           8KB, 16KB, 32KB, 64KB
> >       64          16KB, 32KB, 64KB, 128KB
> > 
> > $B$H$"$j!"$?$7$+$K(J 32bit$B$H(J 64bit$B$,5-:\$5$l$F$$$^$9!#$?$@$7!"(JPLB$B$N%G!<%?(J
> > $B%P%9$NI}$OF1$8%I%-%e%a%s%H$N!V(JTable 2: PLB BRAM Interface Controller
> > Parameters$B!W$K$"$k$h$&$K!"(J64bit$B8GDj$G$9!#(J
> > 
> > table 4$B$N(J 32bit$B$NI=5-$O!"(Jplb$B$G$O$J$/!"$?$H$($P(J 32bit$BI}$N(J fifo$B$J$I$K@\(J
> > $BB3$9$k>l9g$G$O$J$$$G$7$g$&$+!)(J
> > 
> > CPU$B$+$i$N%"%/%;%9I}$H!"(JPLB$B$H(Jbram$B%3%s%H%m!<%i$N@\B3I}$K0c$$$,$"$k$H$$$&(J
> > $B$3$H$G$O$J$$$G$7$g$&$+!)(J
> > -- 
> >         yashi
> > 
> 
> 
>