[Suzaku:01278] Re: Linuxが利用できるSDRAM容量を64MBから32MBに変更したい

email@hidden
2008年 11月 12日 (水) 16:37:23 JST


山本です。

返答が遅くなり申し訳ありません。丁寧なご回答ありがとうございました。
Linuxを32MB領域で動作させることはHermitを変更することでできました。
しかしXilinxのmpmcを使用してSDRAMを16bit幅の32MBにして動かすことはできてい
ません。
bootを開始しないのでSDRAMが正常に動作してないと思われます。
質問の目的はSDRAMの後半32MBを回路との共有メモリにするために、
Linuxのメモリサイズを制限することでしたので、とりあえず私の問題は解決されま
した。
SDRAMをハード的に分割するのは時間ができたときに再トライしてみたいと
思います。ありがとうございました。

email@hidden wrote on 2008/10/31 17:25:15:

> 中島です。

> email@hidden さんは書きました:
> > > SZ410-SIL ユーザの山本と申します。
> > > Linuxが利用できるSDRAM容量を64MBから32MBに変更する方法をご教示くださ
い。
> > >
> > > メーリングリストの「[Suzaku:00662] SZ-130、SDRAMx1で動作」を参考に
> > > linux-2.6.18-
> at9/arch/ppc/platforms/4xx/xparameters/xparameters_sz410-sil.h
> > > の
> > > XPARA_MPMC_DDR2_MPMC_HIGHADDRを0x03FFFFFFから0x01FFFFFFに変更して
> > > makeしてみましたが変更できませんでした。
> > >
> > > よろしくお願いします。
> > >

> SZ410のデフォルトで作業してみました。
> SZ410-SILで作業する場合は適宜変更してください。

>
> * 動作確認環境
> 開発環境 : ISE/EDK10.1 SP3
> ATDE2 v20071018
> FPGAプロジェクト : sz410-20080718
> Hermit           : hermit-at-1.1.18
> Linux カーネル   : linux-2-6-18-at9
> DIST             : atmark-dist-20080314

> * ハードウェアの変更
> DRAMを32Mの1枚使いに変更します。
> SZ410のDRAMコントローラですが、mpmc_sz410というIPコアを使用しています。こ
れは
> SZ410においてDRAMを2枚使う時専用のIPコアで、1枚しか使わない場合は
> Xilinxのmpmcを
> 使用します。

> 1. sz410-20080718/xps_proj.mhsの変更
> 変更点はmhs.patch参照
>
> 2. sz410-20080718/data/xps_proj.ucfの変更
> 変更点はucf.patch参照
>
> 3. bitファイル & xparameters.h作成
> - bitファイル
> sz410-20080718/implementation/download.bit
> - xparameters.h
> sz410-20080718/ppc405_system/include/xparameters.h

>
> * ソフトウェアの変更
> 1. hermi-atの変更
> Linux起動時にhermitからDRAMのパラメータを渡しています。
> 変更点はhermit.patch参照

> 2. linux-kernelの変更
> "ハードウェアの変更 3"で作成した、xparameters.hで以下のファイルを上書
> きする
> linux-2.6.18-at9/arch/ppc/platforms/4xx/xparameters/xparameters_sz410.h
>
> --- C:/suzaku/sz410_20080718/xps_proj.mhs Tue Jul 22 09:55:29 2008
> +++ C:/suzaku/sz410_dram1/xps_proj.mhs Fri Oct 31 16:37:48 2008
> @@ -15,12 +15,12 @@
> PORT SPI_MISO = SPI_MISO, DIR = I, VEC = [0:1]
> PORT SPI_MOSI = SPI_MOSI, DIR = O, VEC = [0:1]
> PORT SPI_SS = SPI_SS, DIR = O, VEC = [0:1]
> - PORT DDR_CLK_OUT = DDR_CLK_OUT, DIR = O, VEC = [0:1]
> - PORT DDR_CLK_OUTn = DDR_CLK_OUTn, DIR = O, VEC = [0:1]
> - PORT DDR_DM = DDR_DM, DIR = O, VEC = [0:3]
> - PORT DDR_DQ = DDR_DQ, DIR = IO, VEC = [0:31]
> - PORT DDR_DQS = DDR_DQS, DIR = IO, VEC = [0:3]
> - PORT DDR_DQSn = DDR_DQSn, DIR = IO, VEC = [0:3]
> + PORT DDR_CLK_OUT = DDR_CLK_OUT, DIR = O
> + PORT DDR_CLK_OUTn = DDR_CLK_OUTn, DIR = O
> + PORT DDR_DM = DDR_DM, DIR = O, VEC = [0:1]
> + PORT DDR_DQ = DDR_DQ, DIR = IO, VEC = [0:15]
> + PORT DDR_DQS = DDR_DQS, DIR = IO, VEC = [0:1]
> + PORT DDR_DQSn = DDR_DQSn, DIR = IO, VEC = [0:1]
> PORT DDR0_CKE = DDR_CKE, DIR = O, VEC = [0:0]
> PORT DDR0_CSn = DDR_CSn, DIR = O, VEC = [0:0]
> PORT DDR0_ODT = DDR_ODT, DIR = O, VEC = [0:0]
> @@ -29,14 +29,6 @@
> PORT DDR0_WEn = DDR_WEn, DIR = O
> PORT DDR0_Addr = DDR_Addr, DIR = O, VEC = [0:12]
> PORT DDR0_BankAddr = DDR_BankAddr, DIR = O, VEC = [0:1]
> - PORT DDR1_CKE = DDR_CKE_2, DIR = O, VEC = [0:0]
> - PORT DDR1_CSn = DDR_CSn_2, DIR = O, VEC = [0:0]
> - PORT DDR1_ODT = DDR_ODT_2, DIR = O, VEC = [0:0]
> - PORT DDR1_RASn = DDR_RASn_2, DIR = O
> - PORT DDR1_CASn = DDR_CASn_2, DIR = O
> - PORT DDR1_WEn = DDR_WEn_2, DIR = O
> - PORT DDR1_Addr = DDR_Addr_2, DIR = O, VEC = [0:12]
> - PORT DDR1_BankAddr = DDR_BankAddr_2, DIR = O, VEC = [0:1]
> PORT MII_TXD_0 = MII_TXD_0, DIR = O, VEC = [3:0]
> PORT MII_TX_EN_0 = MII_TX_EN_0, DIR = O
> PORT MII_TX_ER_0 = MII_TX_ER_0, DIR = I
> @@ -125,7 +117,7 @@

> BEGIN jtagppc_cntlr
> PARAMETER INSTANCE = jtagppc
> - PARAMETER HW_VER = 2.01.a
> + PARAMETER HW_VER = 2.01.c
> BUS_INTERFACE JTAGPPC0 = jtagppc_0
> END
>
> @@ -186,7 +178,7 @@

> BEGIN plb_v46
> PARAMETER INSTANCE = plb_peripheral
> - PARAMETER HW_VER = 1.02.a
> + PARAMETER HW_VER = 1.03.a
> PARAMETER C_NUM_CLK_PLB2OPB_REARB = 100
> PORT SYS_Rst = sys_bus_reset
> PORT PLB_Clk = sys_clk_s
> @@ -254,16 +246,16 @@
> PORT Out2 = FPGA_RESET_EN_w
> END

> -BEGIN mpmc_sz410
> +BEGIN mpmc
> PARAMETER INSTANCE = mpmc_ddr2
> - PARAMETER HW_VER = 2.00.a
> + PARAMETER HW_VER = 4.03.a
> PARAMETER C_MEM_PARTNO = MT47H16M16-37E
> PARAMETER C_MPMC_CLK0_PERIOD_PS = 5714
> PARAMETER C_MPMC_BASEADDR = 0x00000000
> - PARAMETER C_MPMC_HIGHADDR = 0x03FFFFFF
> - PARAMETER C_MEM_DATA_WIDTH = 32
> + PARAMETER C_MPMC_HIGHADDR = 0x01FFFFFF
> + PARAMETER C_MEM_DATA_WIDTH = 16
> PARAMETER C_DDR2_DQSN_ENABLE = 1
> - PARAMETER C_MEM_CLK_WIDTH = 2
> + PARAMETER C_MEM_CLK_WIDTH = 1
> BUS_INTERFACE SPLB0 = plb_memory
> PORT MPMC_Clk90 = DDR_SDRAM_64Mx32_mpmc_clk_90_s
> PORT MPMC_Clk0 = DDR_SDRAM_64Mx32_mpmc_clk_0_s
> @@ -280,14 +272,6 @@
> PORT DDR2_ODT = DDR_ODT
> PORT DDR2_CS_n = DDR_CSn
> PORT DDR2_CE = DDR_CKE
> - PORT DDR2_Addr_2 = DDR_Addr_2
> - PORT DDR2_BankAddr_2 = DDR_BankAddr_2
> - PORT DDR2_WE_n_2 = DDR_WEn_2
> - PORT DDR2_CAS_n_2 = DDR_CASn_2
> - PORT DDR2_RAS_n_2 = DDR_RASn_2
> - PORT DDR2_ODT_2 = DDR_ODT_2
> - PORT DDR2_CS_n_2 = DDR_CSn_2
> - PORT DDR2_CE_2 = DDR_CKE_2
> PORT DDR2_Clk_n = DDR_CLK_OUTn
> PORT DDR2_Clk = DDR_CLK_OUT
> PORT MPMC_Rst = sys_bus_reset
> @@ -295,7 +279,7 @@

> BEGIN plb_v46
> PARAMETER INSTANCE = plb_memory
> - PARAMETER HW_VER = 1.02.a
> + PARAMETER HW_VER = 1.03.a
> PORT SYS_Rst = sys_bus_reset
> PORT PLB_Clk = clk_ddr
> END
>
> --- C:/suzaku/sz410-20080718/data/xps_proj.ucf Tue Jul 22 09:55:29 2008
> +++ C:/suzaku/sz410_dram1/data/xps_proj.ucf Fri Oct 31 16:26:53 2008
> @@ -38,8 +38,8 @@

> # DDR2 SDRAM D0 - D15

> -Net DDR_CLK_OUT<1>   LOC = A16 | IOSTANDARD = DIFF_SSTL18_II;
> -Net DDR_CLK_OUTn<1>  LOC = B16 | IOSTANDARD = DIFF_SSTL18_II;
> +Net DDR_CLK_OUT      LOC = A16 | IOSTANDARD = DIFF_SSTL18_II;
> +Net DDR_CLK_OUTn     LOC = B16 | IOSTANDARD = DIFF_SSTL18_II;
> Net DDR0_CKE<0>      LOC = J18 | IOSTANDARD = SSTL18_I;
> Net DDR0_CSn<0>      LOC = J17 | IOSTANDARD = SSTL18_I;
> Net DDR0_ODT<0>      LOC = C15 | IOSTANDARD = SSTL18_I;
> @@ -63,80 +63,32 @@
> Net DDR0_BankAddr<1> LOC = A15 | IOSTANDARD = SSTL18_I;
> Net DDR0_BankAddr<0> LOC = B15 | IOSTANDARD = SSTL18_I;
>
> -Net DDR_DM<3>        LOC = F17 | IOSTANDARD = SSTL18_I;
> -Net DDR_DQS<3>       LOC = B19 | IOSTANDARD = DIFF_SSTL18_II;
> -Net DDR_DQSn<3>      LOC = C20 | IOSTANDARD = DIFF_SSTL18_II;
> -Net DDR_DQ<31>       LOC = A18 | IOSTANDARD = SSTL18_II;
> -Net DDR_DQ<30>       LOC = E16 | IOSTANDARD = SSTL18_II;
> -Net DDR_DQ<29>       LOC = C18 | IOSTANDARD = SSTL18_II;
> -Net DDR_DQ<28>       LOC = D17 | IOSTANDARD = SSTL18_II;
> -Net DDR_DQ<27>       LOC = F16 | IOSTANDARD = SSTL18_II;
> -Net DDR_DQ<26>       LOC = B18 | IOSTANDARD = SSTL18_II;
> -Net DDR_DQ<25>       LOC = D18 | IOSTANDARD = SSTL18_II;
> -Net DDR_DQ<24>       LOC = C19 | IOSTANDARD = SSTL18_II;
> -
> -Net DDR_DM<2>        LOC = G19 | IOSTANDARD = SSTL18_I;
> -Net DDR_DQS<2>       LOC = F18 | IOSTANDARD = DIFF_SSTL18_II;
> -Net DDR_DQSn<2>      LOC = E18 | IOSTANDARD = DIFF_SSTL18_II;
> -Net DDR_DQ<23>       LOC = F20 | IOSTANDARD = SSTL18_II;
> -Net DDR_DQ<22>       LOC = D19 | IOSTANDARD = SSTL18_II;
> -Net DDR_DQ<21>       LOC = H16 | IOSTANDARD = SSTL18_II;
> -Net DDR_DQ<20>       LOC = G16 | IOSTANDARD = SSTL18_II;
> -Net DDR_DQ<19>       LOC = G17 | IOSTANDARD = SSTL18_II;
> -Net DDR_DQ<18>       LOC = E20 | IOSTANDARD = SSTL18_II;
> -Net DDR_DQ<17>       LOC = F19 | IOSTANDARD = SSTL18_II;
> -Net DDR_DQ<16>       LOC = H17 | IOSTANDARD = SSTL18_II;
> +Net DDR_DM<1>        LOC = F17 | IOSTANDARD = SSTL18_I;
> +Net DDR_DQS<1>       LOC = B19 | IOSTANDARD = DIFF_SSTL18_II;
> +Net DDR_DQSn<1>      LOC = C20 | IOSTANDARD = DIFF_SSTL18_II;
> +Net DDR_DQ<15>       LOC = A18 | IOSTANDARD = SSTL18_II;
> +Net DDR_DQ<14>       LOC = E16 | IOSTANDARD = SSTL18_II;
> +Net DDR_DQ<13>       LOC = C18 | IOSTANDARD = SSTL18_II;
> +Net DDR_DQ<12>       LOC = D17 | IOSTANDARD = SSTL18_II;
> +Net DDR_DQ<11>       LOC = F16 | IOSTANDARD = SSTL18_II;
> +Net DDR_DQ<10>       LOC = B18 | IOSTANDARD = SSTL18_II;
> +Net DDR_DQ<9>       LOC = D18 | IOSTANDARD = SSTL18_II;
> +Net DDR_DQ<8>       LOC = C19 | IOSTANDARD = SSTL18_II;
> +
> +Net DDR_DM<0>        LOC = G19 | IOSTANDARD = SSTL18_I;
> +Net DDR_DQS<0>       LOC = F18 | IOSTANDARD = DIFF_SSTL18_II;
> +Net DDR_DQSn<0>      LOC = E18 | IOSTANDARD = DIFF_SSTL18_II;
> +Net DDR_DQ<7>       LOC = F20 | IOSTANDARD = SSTL18_II;
> +Net DDR_DQ<6>       LOC = D19 | IOSTANDARD = SSTL18_II;
> +Net DDR_DQ<5>       LOC = H16 | IOSTANDARD = SSTL18_II;
> +Net DDR_DQ<4>       LOC = G16 | IOSTANDARD = SSTL18_II;
> +Net DDR_DQ<3>       LOC = G17 | IOSTANDARD = SSTL18_II;
> +Net DDR_DQ<2>       LOC = E20 | IOSTANDARD = SSTL18_II;
> +Net DDR_DQ<1>       LOC = F19 | IOSTANDARD = SSTL18_II;
> +Net DDR_DQ<0>       LOC = H17 | IOSTANDARD = SSTL18_II;

> # DDR2 SDRAM D16 - D31

> -Net DDR_CLK_out<0>   LOC = M20 | IOSTANDARD = DIFF_SSTL18_II;
> -Net DDR_CLK_outn<0>  LOC = L20 | IOSTANDARD = DIFF_SSTL18_II;
> -Net DDR1_CKE<0>      LOC = P19 | IOSTANDARD = SSTL18_I;
> -Net DDR1_CSn<0>      LOC = T17 | IOSTANDARD = SSTL18_I;
> -Net DDR1_ODT<0>      LOC = U15 | IOSTANDARD = SSTL18_I;
> -Net DDR1_RASn        LOC = T15 | IOSTANDARD = SSTL18_I;
> -Net DDR1_CASn        LOC = U19 | IOSTANDARD = SSTL18_I;
> -Net DDR1_WEn         LOC = R16 | IOSTANDARD = SSTL18_I;
> -
> -Net DDR1_Addr<12>    LOC = W17 | IOSTANDARD = SSTL18_I;
> -Net DDR1_Addr<11>    LOC = R15 | IOSTANDARD = SSTL18_I;
> -Net DDR1_Addr<10>    LOC = V17 | IOSTANDARD = SSTL18_I;
> -Net DDR1_Addr<9>     LOC = U18 | IOSTANDARD = SSTL18_I;
> -Net DDR1_Addr<8>     LOC = W18 | IOSTANDARD = SSTL18_I;
> -Net DDR1_Addr<7>     LOC = Y17 | IOSTANDARD = SSTL18_I;
> -Net DDR1_Addr<6>     LOC = V19 | IOSTANDARD = SSTL18_I;
> -Net DDR1_Addr<5>     LOC = R19 | IOSTANDARD = SSTL18_I;
> -Net DDR1_Addr<4>     LOC = U16 | IOSTANDARD = SSTL18_I;
> -Net DDR1_Addr<3>     LOC = U17 | IOSTANDARD = SSTL18_I;
> -Net DDR1_Addr<2>     LOC = T18 | IOSTANDARD = SSTL18_I;
> -Net DDR1_Addr<1>     LOC = W19 | IOSTANDARD = SSTL18_I;
> -Net DDR1_Addr<0>     LOC = V18 | IOSTANDARD = SSTL18_I;
> -Net DDR1_BankAddr<1> LOC = R18 | IOSTANDARD = SSTL18_I;
> -Net DDR1_BankAddr<0> LOC = R17 | IOSTANDARD = SSTL18_I;
> -
> -Net DDR_DM<1>        LOC = M15 | IOSTANDARD = SSTL18_I;
> -Net DDR_DQS<1>       LOC = M17 | IOSTANDARD = DIFF_SSTL18_II;
> -Net DDR_DQSn<1>      LOC = M18 | IOSTANDARD = DIFF_SSTL18_II;
> -Net DDR_DQ<15>       LOC = P17 | IOSTANDARD = SSTL18_II;
> -Net DDR_DQ<14>       LOC = M19 | IOSTANDARD = SSTL18_II;
> -Net DDR_DQ<13>       LOC = N19 | IOSTANDARD = SSTL18_II;
> -Net DDR_DQ<12>       LOC = N17 | IOSTANDARD = SSTL18_II;
> -Net DDR_DQ<11>       LOC = N16 | IOSTANDARD = SSTL18_II;
> -Net DDR_DQ<10>       LOC = N18 | IOSTANDARD = SSTL18_II;
> -Net DDR_DQ<9>        LOC = M16 | IOSTANDARD = SSTL18_II;
> -Net DDR_DQ<8>        LOC = P16 | IOSTANDARD = SSTL18_II;
> -
> -Net DDR_DM<0>        LOC = H20 | IOSTANDARD = SSTL18_I;
> -Net DDR_DQS<0>       LOC = K18 | IOSTANDARD = DIFF_SSTL18_II;
> -Net DDR_DQSn<0>      LOC = K19 | IOSTANDARD = DIFF_SSTL18_II;
> -Net DDR_DQ<7>        LOC = J19 | IOSTANDARD = SSTL18_II;
> -Net DDR_DQ<6>        LOC = K20 | IOSTANDARD = SSTL18_II;
> -Net DDR_DQ<5>        LOC = K17 | IOSTANDARD = SSTL18_II;
> -Net DDR_DQ<4>        LOC = K16 | IOSTANDARD = SSTL18_II;
> -Net DDR_DQ<3>        LOC = J16 | IOSTANDARD = SSTL18_II;
> -Net DDR_DQ<2>        LOC = J15 | IOSTANDARD = SSTL18_II;
> -Net DDR_DQ<1>        LOC = G20 | IOSTANDARD = SSTL18_II;
> -Net DDR_DQ<0>        LOC = H18 | IOSTANDARD = SSTL18_II;

> # TEMAC MII

>
> diff --git a/src/target/suzaku/linux.c b/src/target/suzaku/linux.c
> index 1b2446a..4c1f76e 100644
> --- a/src/target/suzaku/linux.c
> +++ b/src/target/suzaku/linux.c
> @@ -50,7 +50,7 @@ bd_t bi_sz310 = {
> .bi_busfreq = 3686400 * 18 * 4 / 4, /*  66.3552MHz */
> };
> bd_t bi_sz410 = {
> -        .bi_memsize = 1024 * 1024 * 64,     /*  64     MiB */
> +        .bi_memsize = 1024 * 1024 * 32,     /*  32     MiB */
> .bi_intfreq = 100000000 * 7 / 2,    /* 350.0000MHz */
> .bi_busfreq = 100000000 * 7 / 8,    /*  87.5000MHz */
> };
>
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