[Suzaku:01633] Re: Dフリップフロップ

Keichi KAWAOKA email@hidden
2009年 8月 26日 (水) 20:37:58 JST


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$B!V(BSUZAKU$B%9%?!<%?!<%-%C%H%,%$%I(B FPGA$BJT!W(B
http://suzaku.atmark-techno.com/files/downloads/suzaku-starter-kit/suzaku_starter_kit_guide_fpga_ja-2.4.6.pdf
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$B>e1r!!9d(B $B$5$s$O=q$-$^$7$?(B:
> uezono$B$H?=$7$^$9!#!J(BFPGA$BNr!!0l%v7nL$K~!K(B
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> 
> $B-!$3$N$h$&$J;H$$J}$O$G$-$J$$$N$G$7$g$&$+!)(B
> $B-";H$($k$H$7$?$i!$$I$N$h$&$KBP=h$9$l$P$h$m$7$$$G$7$g$&$+!#(B
> $B!J%$%s%W%j%a%s%F!<%7%g%s(B $B%*%W%7%g%s$r;HMQ(B
> $B!!(BXST
> $B!!(B-keep_hierarchy No
> $B!!(B-read_cores No
> $B!!!!$H$"$k$N$G$9$,!&!&!&!K(B
> 
> $B$465<x$$$?$@$1$k$H9,$$$G$9!#(B
> 
> $B!]!]!]!]!]!]!]!]!]!]!]!]5-!]!]!]!]!]!]!]!]!]!]!]!]!]!](B
> 
> $B%W%m%0%i%`!]!]!]!]!]!]!]!]!]!]!]!]!]!]!]!]!](B
> entity top is
> Port (
> $B!!!!(BnLE0 : out STD_LOGIC;
> $B!!!!(BnSW0 : in STD_LOGIC;
> $B!!!!(BnSW1 : in STD_LOGIC
> );
> end top;
> 
> --$B%"!<%-%F%/%A%c(B($B2sO)K\BN(B)
> architecture IMP of top is
> $B!!(Bbegin
> $B!!(Bprocess(nSW1,nSW0)
> $B!!(Bbegin
>  $B!!!!(Bif nSW0='0' then
>   $B!!!!!!!!(BnLE0 <= '0';
>  $B!!!!(Belsif nSW1'event and nSW1='0' then
>   $B!!!!!!!!(BnLE0 <= '1';
>  $B!!!!(Bend if;
> $B!!(Bend process;
> end IMP;
> 
> $B%(%i!<%a%C%;!<%8!]!]!]!]!]!]!]!]!]!]!]!]!]!]!]!]!](B
> ERROR:Place:1018 - A clock IOB / clock component pair have been found 
> that are not placed at an optimal clock IOB /
> 
> Started : "Generate Programming File".
> ERROR:PhysDesignRules:10 - The network <nSW0_IBUF> is completely unrouted.
> ERROR:PhysDesignRules:10 - The network <nSW1_BUFGP/IBUFG> is completely
>   unrouted.
> ERROR:PhysDesignRules:10 - The network <nSW1_BUFGP> is completely unrouted.
> ERROR:PhysDesignRules:10 - The network <GLOBAL_LOGIC1> is completely 
> unrouted.
> ERROR:Bitgen:25 - DRC detected 4 errors and 0 warnings.
> 
> 
> $B!]!]!]!]!]!]!]!]!]!]!]!]!]!]!](B
> $BEvJ}4D6-(B
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> $B!&(BSZ-130SIL
> $B!JB>$KI,MW$J>pJs$,$"$j$^$7$?$i65$($F$/$@$5$$!K(B
> 
> 
> 
> ------------------------------------------------------------------------
> 
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> suzaku mailing list
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