--- C:/suzaku/sz410-20080718/data/xps_proj.ucf	Tue Jul 22 09:55:29 2008
+++ C:/suzaku/sz410_dram1/data/xps_proj.ucf	Fri Oct 31 16:26:53 2008
@@ -38,8 +38,8 @@
 
 # DDR2 SDRAM D0 - D15
 
-Net DDR_CLK_OUT<1>   LOC = A16 | IOSTANDARD = DIFF_SSTL18_II;
-Net DDR_CLK_OUTn<1>  LOC = B16 | IOSTANDARD = DIFF_SSTL18_II;
+Net DDR_CLK_OUT      LOC = A16 | IOSTANDARD = DIFF_SSTL18_II;
+Net DDR_CLK_OUTn     LOC = B16 | IOSTANDARD = DIFF_SSTL18_II;
 Net DDR0_CKE<0>      LOC = J18 | IOSTANDARD = SSTL18_I;
 Net DDR0_CSn<0>      LOC = J17 | IOSTANDARD = SSTL18_I;
 Net DDR0_ODT<0>      LOC = C15 | IOSTANDARD = SSTL18_I;
@@ -63,80 +63,32 @@
 Net DDR0_BankAddr<1> LOC = A15 | IOSTANDARD = SSTL18_I;
 Net DDR0_BankAddr<0> LOC = B15 | IOSTANDARD = SSTL18_I;
 
-Net DDR_DM<3>        LOC = F17 | IOSTANDARD = SSTL18_I;
-Net DDR_DQS<3>       LOC = B19 | IOSTANDARD = DIFF_SSTL18_II;
-Net DDR_DQSn<3>      LOC = C20 | IOSTANDARD = DIFF_SSTL18_II;
-Net DDR_DQ<31>       LOC = A18 | IOSTANDARD = SSTL18_II;
-Net DDR_DQ<30>       LOC = E16 | IOSTANDARD = SSTL18_II;
-Net DDR_DQ<29>       LOC = C18 | IOSTANDARD = SSTL18_II;
-Net DDR_DQ<28>       LOC = D17 | IOSTANDARD = SSTL18_II;
-Net DDR_DQ<27>       LOC = F16 | IOSTANDARD = SSTL18_II;
-Net DDR_DQ<26>       LOC = B18 | IOSTANDARD = SSTL18_II;
-Net DDR_DQ<25>       LOC = D18 | IOSTANDARD = SSTL18_II;
-Net DDR_DQ<24>       LOC = C19 | IOSTANDARD = SSTL18_II;
-
-Net DDR_DM<2>        LOC = G19 | IOSTANDARD = SSTL18_I;
-Net DDR_DQS<2>       LOC = F18 | IOSTANDARD = DIFF_SSTL18_II;
-Net DDR_DQSn<2>      LOC = E18 | IOSTANDARD = DIFF_SSTL18_II;
-Net DDR_DQ<23>       LOC = F20 | IOSTANDARD = SSTL18_II;
-Net DDR_DQ<22>       LOC = D19 | IOSTANDARD = SSTL18_II;
-Net DDR_DQ<21>       LOC = H16 | IOSTANDARD = SSTL18_II;
-Net DDR_DQ<20>       LOC = G16 | IOSTANDARD = SSTL18_II;
-Net DDR_DQ<19>       LOC = G17 | IOSTANDARD = SSTL18_II;
-Net DDR_DQ<18>       LOC = E20 | IOSTANDARD = SSTL18_II;
-Net DDR_DQ<17>       LOC = F19 | IOSTANDARD = SSTL18_II;
-Net DDR_DQ<16>       LOC = H17 | IOSTANDARD = SSTL18_II;
+Net DDR_DM<1>        LOC = F17 | IOSTANDARD = SSTL18_I;
+Net DDR_DQS<1>       LOC = B19 | IOSTANDARD = DIFF_SSTL18_II;
+Net DDR_DQSn<1>      LOC = C20 | IOSTANDARD = DIFF_SSTL18_II;
+Net DDR_DQ<15>       LOC = A18 | IOSTANDARD = SSTL18_II;
+Net DDR_DQ<14>       LOC = E16 | IOSTANDARD = SSTL18_II;
+Net DDR_DQ<13>       LOC = C18 | IOSTANDARD = SSTL18_II;
+Net DDR_DQ<12>       LOC = D17 | IOSTANDARD = SSTL18_II;
+Net DDR_DQ<11>       LOC = F16 | IOSTANDARD = SSTL18_II;
+Net DDR_DQ<10>       LOC = B18 | IOSTANDARD = SSTL18_II;
+Net DDR_DQ<9>       LOC = D18 | IOSTANDARD = SSTL18_II;
+Net DDR_DQ<8>       LOC = C19 | IOSTANDARD = SSTL18_II;
+
+Net DDR_DM<0>        LOC = G19 | IOSTANDARD = SSTL18_I;
+Net DDR_DQS<0>       LOC = F18 | IOSTANDARD = DIFF_SSTL18_II;
+Net DDR_DQSn<0>      LOC = E18 | IOSTANDARD = DIFF_SSTL18_II;
+Net DDR_DQ<7>       LOC = F20 | IOSTANDARD = SSTL18_II;
+Net DDR_DQ<6>       LOC = D19 | IOSTANDARD = SSTL18_II;
+Net DDR_DQ<5>       LOC = H16 | IOSTANDARD = SSTL18_II;
+Net DDR_DQ<4>       LOC = G16 | IOSTANDARD = SSTL18_II;
+Net DDR_DQ<3>       LOC = G17 | IOSTANDARD = SSTL18_II;
+Net DDR_DQ<2>       LOC = E20 | IOSTANDARD = SSTL18_II;
+Net DDR_DQ<1>       LOC = F19 | IOSTANDARD = SSTL18_II;
+Net DDR_DQ<0>       LOC = H17 | IOSTANDARD = SSTL18_II;
 
 # DDR2 SDRAM D16 - D31
 
-Net DDR_CLK_out<0>   LOC = M20 | IOSTANDARD = DIFF_SSTL18_II;
-Net DDR_CLK_outn<0>  LOC = L20 | IOSTANDARD = DIFF_SSTL18_II;
-Net DDR1_CKE<0>      LOC = P19 | IOSTANDARD = SSTL18_I;
-Net DDR1_CSn<0>      LOC = T17 | IOSTANDARD = SSTL18_I;
-Net DDR1_ODT<0>      LOC = U15 | IOSTANDARD = SSTL18_I;
-Net DDR1_RASn        LOC = T15 | IOSTANDARD = SSTL18_I;
-Net DDR1_CASn        LOC = U19 | IOSTANDARD = SSTL18_I;
-Net DDR1_WEn         LOC = R16 | IOSTANDARD = SSTL18_I;
-
-Net DDR1_Addr<12>    LOC = W17 | IOSTANDARD = SSTL18_I;
-Net DDR1_Addr<11>    LOC = R15 | IOSTANDARD = SSTL18_I;
-Net DDR1_Addr<10>    LOC = V17 | IOSTANDARD = SSTL18_I;
-Net DDR1_Addr<9>     LOC = U18 | IOSTANDARD = SSTL18_I;
-Net DDR1_Addr<8>     LOC = W18 | IOSTANDARD = SSTL18_I;
-Net DDR1_Addr<7>     LOC = Y17 | IOSTANDARD = SSTL18_I;
-Net DDR1_Addr<6>     LOC = V19 | IOSTANDARD = SSTL18_I;
-Net DDR1_Addr<5>     LOC = R19 | IOSTANDARD = SSTL18_I;
-Net DDR1_Addr<4>     LOC = U16 | IOSTANDARD = SSTL18_I;
-Net DDR1_Addr<3>     LOC = U17 | IOSTANDARD = SSTL18_I;
-Net DDR1_Addr<2>     LOC = T18 | IOSTANDARD = SSTL18_I;
-Net DDR1_Addr<1>     LOC = W19 | IOSTANDARD = SSTL18_I;
-Net DDR1_Addr<0>     LOC = V18 | IOSTANDARD = SSTL18_I;
-Net DDR1_BankAddr<1> LOC = R18 | IOSTANDARD = SSTL18_I;
-Net DDR1_BankAddr<0> LOC = R17 | IOSTANDARD = SSTL18_I;
-
-Net DDR_DM<1>        LOC = M15 | IOSTANDARD = SSTL18_I;
-Net DDR_DQS<1>       LOC = M17 | IOSTANDARD = DIFF_SSTL18_II;
-Net DDR_DQSn<1>      LOC = M18 | IOSTANDARD = DIFF_SSTL18_II;
-Net DDR_DQ<15>       LOC = P17 | IOSTANDARD = SSTL18_II;
-Net DDR_DQ<14>       LOC = M19 | IOSTANDARD = SSTL18_II;
-Net DDR_DQ<13>       LOC = N19 | IOSTANDARD = SSTL18_II;
-Net DDR_DQ<12>       LOC = N17 | IOSTANDARD = SSTL18_II;
-Net DDR_DQ<11>       LOC = N16 | IOSTANDARD = SSTL18_II;
-Net DDR_DQ<10>       LOC = N18 | IOSTANDARD = SSTL18_II;
-Net DDR_DQ<9>        LOC = M16 | IOSTANDARD = SSTL18_II;
-Net DDR_DQ<8>        LOC = P16 | IOSTANDARD = SSTL18_II;
-
-Net DDR_DM<0>        LOC = H20 | IOSTANDARD = SSTL18_I;
-Net DDR_DQS<0>       LOC = K18 | IOSTANDARD = DIFF_SSTL18_II;
-Net DDR_DQSn<0>      LOC = K19 | IOSTANDARD = DIFF_SSTL18_II;
-Net DDR_DQ<7>        LOC = J19 | IOSTANDARD = SSTL18_II;
-Net DDR_DQ<6>        LOC = K20 | IOSTANDARD = SSTL18_II;
-Net DDR_DQ<5>        LOC = K17 | IOSTANDARD = SSTL18_II;
-Net DDR_DQ<4>        LOC = K16 | IOSTANDARD = SSTL18_II;
-Net DDR_DQ<3>        LOC = J16 | IOSTANDARD = SSTL18_II;
-Net DDR_DQ<2>        LOC = J15 | IOSTANDARD = SSTL18_II;
-Net DDR_DQ<1>        LOC = G20 | IOSTANDARD = SSTL18_II;
-Net DDR_DQ<0>        LOC = H18 | IOSTANDARD = SSTL18_II;
 
 # TEMAC MII
 
