--- C:/suzaku/sz410_20080718/xps_proj.mhs	Tue Jul 22 09:55:29 2008
+++ C:/suzaku/sz410_dram1/xps_proj.mhs	Fri Oct 31 16:37:48 2008
@@ -15,12 +15,12 @@
  PORT SPI_MISO = SPI_MISO, DIR = I, VEC = [0:1]
  PORT SPI_MOSI = SPI_MOSI, DIR = O, VEC = [0:1]
  PORT SPI_SS = SPI_SS, DIR = O, VEC = [0:1]
- PORT DDR_CLK_OUT = DDR_CLK_OUT, DIR = O, VEC = [0:1]
- PORT DDR_CLK_OUTn = DDR_CLK_OUTn, DIR = O, VEC = [0:1]
- PORT DDR_DM = DDR_DM, DIR = O, VEC = [0:3]
- PORT DDR_DQ = DDR_DQ, DIR = IO, VEC = [0:31]
- PORT DDR_DQS = DDR_DQS, DIR = IO, VEC = [0:3]
- PORT DDR_DQSn = DDR_DQSn, DIR = IO, VEC = [0:3]
+ PORT DDR_CLK_OUT = DDR_CLK_OUT, DIR = O
+ PORT DDR_CLK_OUTn = DDR_CLK_OUTn, DIR = O
+ PORT DDR_DM = DDR_DM, DIR = O, VEC = [0:1]
+ PORT DDR_DQ = DDR_DQ, DIR = IO, VEC = [0:15]
+ PORT DDR_DQS = DDR_DQS, DIR = IO, VEC = [0:1]
+ PORT DDR_DQSn = DDR_DQSn, DIR = IO, VEC = [0:1]
  PORT DDR0_CKE = DDR_CKE, DIR = O, VEC = [0:0]
  PORT DDR0_CSn = DDR_CSn, DIR = O, VEC = [0:0]
  PORT DDR0_ODT = DDR_ODT, DIR = O, VEC = [0:0]
@@ -29,14 +29,6 @@
  PORT DDR0_WEn = DDR_WEn, DIR = O
  PORT DDR0_Addr = DDR_Addr, DIR = O, VEC = [0:12]
  PORT DDR0_BankAddr = DDR_BankAddr, DIR = O, VEC = [0:1]
- PORT DDR1_CKE = DDR_CKE_2, DIR = O, VEC = [0:0]
- PORT DDR1_CSn = DDR_CSn_2, DIR = O, VEC = [0:0]
- PORT DDR1_ODT = DDR_ODT_2, DIR = O, VEC = [0:0]
- PORT DDR1_RASn = DDR_RASn_2, DIR = O
- PORT DDR1_CASn = DDR_CASn_2, DIR = O
- PORT DDR1_WEn = DDR_WEn_2, DIR = O
- PORT DDR1_Addr = DDR_Addr_2, DIR = O, VEC = [0:12]
- PORT DDR1_BankAddr = DDR_BankAddr_2, DIR = O, VEC = [0:1]
  PORT MII_TXD_0 = MII_TXD_0, DIR = O, VEC = [3:0]
  PORT MII_TX_EN_0 = MII_TX_EN_0, DIR = O
  PORT MII_TX_ER_0 = MII_TX_ER_0, DIR = I
@@ -125,7 +117,7 @@
 
 BEGIN jtagppc_cntlr
  PARAMETER INSTANCE = jtagppc
- PARAMETER HW_VER = 2.01.a
+ PARAMETER HW_VER = 2.01.c
  BUS_INTERFACE JTAGPPC0 = jtagppc_0
 END
 
@@ -186,7 +178,7 @@
 
 BEGIN plb_v46
  PARAMETER INSTANCE = plb_peripheral
- PARAMETER HW_VER = 1.02.a
+ PARAMETER HW_VER = 1.03.a
  PARAMETER C_NUM_CLK_PLB2OPB_REARB = 100
  PORT SYS_Rst = sys_bus_reset
  PORT PLB_Clk = sys_clk_s
@@ -254,16 +246,16 @@
  PORT Out2 = FPGA_RESET_EN_w
 END
 
-BEGIN mpmc_sz410
+BEGIN mpmc
  PARAMETER INSTANCE = mpmc_ddr2
- PARAMETER HW_VER = 2.00.a
+ PARAMETER HW_VER = 4.03.a
  PARAMETER C_MEM_PARTNO = MT47H16M16-37E
  PARAMETER C_MPMC_CLK0_PERIOD_PS = 5714
  PARAMETER C_MPMC_BASEADDR = 0x00000000
- PARAMETER C_MPMC_HIGHADDR = 0x03FFFFFF
- PARAMETER C_MEM_DATA_WIDTH = 32
+ PARAMETER C_MPMC_HIGHADDR = 0x01FFFFFF
+ PARAMETER C_MEM_DATA_WIDTH = 16
  PARAMETER C_DDR2_DQSN_ENABLE = 1
- PARAMETER C_MEM_CLK_WIDTH = 2
+ PARAMETER C_MEM_CLK_WIDTH = 1
  BUS_INTERFACE SPLB0 = plb_memory
  PORT MPMC_Clk90 = DDR_SDRAM_64Mx32_mpmc_clk_90_s
  PORT MPMC_Clk0 = DDR_SDRAM_64Mx32_mpmc_clk_0_s
@@ -280,14 +272,6 @@
  PORT DDR2_ODT = DDR_ODT
  PORT DDR2_CS_n = DDR_CSn
  PORT DDR2_CE = DDR_CKE
- PORT DDR2_Addr_2 = DDR_Addr_2
- PORT DDR2_BankAddr_2 = DDR_BankAddr_2
- PORT DDR2_WE_n_2 = DDR_WEn_2
- PORT DDR2_CAS_n_2 = DDR_CASn_2
- PORT DDR2_RAS_n_2 = DDR_RASn_2
- PORT DDR2_ODT_2 = DDR_ODT_2
- PORT DDR2_CS_n_2 = DDR_CSn_2
- PORT DDR2_CE_2 = DDR_CKE_2
  PORT DDR2_Clk_n = DDR_CLK_OUTn
  PORT DDR2_Clk = DDR_CLK_OUT
  PORT MPMC_Rst = sys_bus_reset
@@ -295,7 +279,7 @@
 
 BEGIN plb_v46
  PARAMETER INSTANCE = plb_memory
- PARAMETER HW_VER = 1.02.a
+ PARAMETER HW_VER = 1.03.a
  PORT SYS_Rst = sys_bus_reset
  PORT PLB_Clk = clk_ddr
 END
