[Armadillo:03816] Re: IMX31 GPT control Register のOM3ビットについて

[Takenoshita Koyo]

> たとえば、100に設定したときと、
> 101に設定したときではなにが異なるのでしょう? 

MCIMX31 and MCIMX31L Applications Processors Reference Manual MCIMX31RM
Table 34-6. GPT Control Register Field Descriptions
> When OM3 is programmed as 1xx (active low pulse), the output pin is set
> to one, immediately on the next input clock, and the low pulse occurs when there is a compare event.

"1xx"とあるので、
> 100 Generate a single count duration pulse on output
> 101 Generate a single count duration pulse on output
> 110 Generate a single count duration pulse on output
> 111 Generate a single count duration pulse on output 
で全て同じ動作になるのではないでしょうか？

-- 
Koyo Takenoshita