[Suzaku-en:00217] kernel boot error with uClinux-dist-20051110-suzaku3, solved

Lars email@hidden
Thu Oct 5 17:45:13 JST 2006


After upgrading the FPGA configuration to a version
built with newer tools my board now boots OK with
uClinux-dist-20051110-suzaku3. I used
sz030-20060811/default_bit_file/fpga-sz030.mcs from
Suzaku portal site /fpga_proj/8.1i/sz030.

Looks like you need the latest FPGA config too use the
latest uClinux dist.

/Lars

> Till: email@hidden
> 
> Hello Cheney and others,
> 
> Same problem here. Same board and setup as Cheney
> (see
> below). Images made with
> uClinux-dist-20040408-suzaku6
> works. I've added two GPIO:s to the FPGA.
> 
> With netflash the new image has to be force loaded
> with the -H switch because of product name change?
> 
> /Lars Peterson
> 
> This is the the address map and pinout file:
> 
> Address Map for Processor microblaze_i
>   (0x00000000-0x00001fff) d_lmb_bram_if_cntlr
> d_lmb_v10
>   (0x00000000-0x00001fff) i_lmb_bram_if_cntlr
> i_lmb_v10
>   (0x80000000-0x80ffffff) sdram_controller	d_opb_v20
>   (0xff000000-0xff7fffff) system_memcon	d_opb_v20
>   (0xffe00000-0xffefffff) system_memcon	d_opb_v20
>   (0xffff0000-0xffff01ff) system_memcon	d_opb_v20
>   (0xffff1000-0xffff10ff) system_timer	d_opb_v20
>   (0xffff2000-0xffff20ff) console_uart	d_opb_v20
>   (0xffff3000-0xffff30ff) system_intc	d_opb_v20
>   (0xffffa000-0xffffa0ff) opb_gpio_0	d_opb_v20
>   (0xffffa100-0xffffa1ff) opb_gpio_1	d_opb_v20
>   (0xffffa200-0xffffa2ff) opb_gpio_2	d_opb_v20
> 
> 
> Net sys_clk PERIOD = 19376 ps;
> 
> #PINLOCK_END
> 
> #PACE: Start of Constraints generated by PACE
> 
> #PACE: Start of PACE I/O Pin Assignments
> NET "BOOTMODE"  LOC = "F3"  ; 
> NET "BUS_REL"  LOC = "M4"  ; 
> NET "BUS_REQ"  LOC = "N1"  ; 
> NET "CNSL_CTSn"  LOC = "E1"  ; 
> NET "CNSL_RTSn"  LOC = "F4"  ; 
> NET "CNSL_RX"  LOC = "E2"  ; 
> NET "CNSL_TX"  LOC = "E4"  ; 
> NET "FLASH_BYTEn"  LOC = "J3"  ; 
> NET "FLASH_CEn"  LOC = "K3"  ; 
> NET "FLASH_OEn"  LOC = "K2"  ; 
> NET "FLASH_RnB"  LOC = "J2"  ; 
> NET "FLASH_WEn"  LOC = "J4"  ; 
> NET "FPGA_RESET_EN"  LOC = "F2"  ; 
> 
> NET "GPIO_IO_1<0>"  LOC = "B11"  ;
> NET "GPIO_IO_1<1>"  LOC = "C11"  ;
> NET "GPIO_IO_1<2>"  LOC = "D10"  ;
> NET "GPIO_IO_1<3>"  LOC = "E10"  ;
> NET "GPIO_IO_1<4>"  LOC = "A10"  ;
> NET "GPIO_IO_1<5>"  LOC = "B10"  ;
> NET "GPIO_IO_1<6>"  LOC = "B16"  ;
> NET "GPIO_IO_1<7>"  LOC = "C16"  ;
> NET "GPIO_IO_1<8>"  LOC = "C15"  ;
> NET "GPIO_IO_1<9>"  LOC = "D14"  ;
> NET "GPIO_IO_1<10>"  LOC = "D15"  ;
> NET "GPIO_IO_1<11>"  LOC = "D16"  ;
> 
> NET "GPIO_IO_2<0>"  LOC = "E13"  ;
> NET "GPIO_IO_2<1>"  LOC = "E14"  ;
> NET "GPIO_IO_2<2>"  LOC = "E15"  ;
> NET "GPIO_IO_2<3>"  LOC = "E16"  ;
> NET "GPIO_IO_2<4>"  LOC = "F12"  ;
> NET "GPIO_IO_2<5>"  LOC = "F13"  ;
> NET "GPIO_IO_2<6>"  LOC = "F15"  ;
> NET "GPIO_IO_2<7>"  LOC = "G12"  ;
> NET "GPIO_IO_2<8>"  LOC = "G13"  ;
> NET "GPIO_IO_2<9>"  LOC = "G14"  ;
> NET "GPIO_IO_2<10>"  LOC = "G15"  ;
> NET "GPIO_IO_2<11>"  LOC = "H13"  ;
> 
> NET "LA<0>"  LOC = "T12"  ; 
> NET "LA<10>"  LOC = "P11"  ; 
> NET "LA<11>"  LOC = "R11"  ; 
> NET "LA<12>"  LOC = "M10"  ; 
> NET "LA<13>"  LOC = "N10"  ; 
> NET "LA<14>"  LOC = "P10"  ; 
> NET "LA<15>"  LOC = "N5"  ; 
> NET "LA<16>"  LOC = "P7"  ; 
> NET "LA<17>"  LOC = "T5"  ; 
> NET "LA<18>"  LOC = "T8"  ; 
> NET "LA<19>"  LOC = "T3"  ; 
> NET "LA<1>"  LOC = "T14"  ; 
> NET "LA<20>"  LOC = "R3"  ; 
> NET "LA<21>"  LOC = "T4"  ; 
> NET "LA<22>"  LOC = "R4"  ; 
> NET "LA<2>"  LOC = "N12"  ; 
> NET "LA<3>"  LOC = "P13"  ; 
> NET "LA<4>"  LOC = "T10"  ; 
> NET "LA<5>"  LOC = "R13"  ; 
> NET "LA<6>"  LOC = "T13"  ; 
> NET "LA<7>"  LOC = "P12"  ; 
> NET "LA<8>"  LOC = "R12"  ; 
> NET "LA<9>"  LOC = "N11"  ; 
> NET "LD<0>"  LOC = "T7"  ; 
> NET "LD<10>"  LOC = "N6"  ; 
> NET "LD<11>"  LOC = "M6"  ; 
> NET "LD<12>"  LOC = "R6"  ; 
> NET "LD<13>"  LOC = "P6"  ; 
> NET "LD<14>"  LOC = "N7"  ; 
> NET "LD<15>"  LOC = "M7"  ; 
> NET "LD<1>"  LOC = "R7"  ; 
> NET "LD<2>"  LOC = "K1"  ; 
> NET "LD<3>"  LOC = "R1"  ; 
> NET "LD<4>"  LOC = "P1"  ; 
> NET "LD<5>"  LOC = "P2"  ; 
> NET "LD<6>"  LOC = "N3"  ; 
> NET "LD<7>"  LOC = "N2"  ; 
> NET "LD<8>"  LOC = "R5"  ; 
> NET "LD<9>"  LOC = "P5"  ; 
> NET "LEDn"  LOC = "G5"  ; 
> NET "MAC_ADSn"  LOC = "D1"  ; 
> NET "MAC_AEN"  LOC = "C1"  ; 
> NET "MAC_ARDY"  LOC = "C3"  ; 
> NET "MAC_BEn<0>"  LOC = "G2"  ; 
> NET "MAC_BEn<1>"  LOC = "J1"  ; 
> NET "MAC_INTR"  LOC = "D2"  ; 
> NET "MAC_RDn"  LOC = "B1"  ; 
> NET "MAC_WRn"  LOC = "C2"  ; 
> NET "RAM_BS<0>"  LOC = "K5"  ; 
> NET "RAM_BS<1>"  LOC = "K4"  ; 
> NET "RAM_CASn"  LOC = "M1"  ; 
> NET "RAM_CKE"  LOC = "L4"  ; 
> NET "RAM_CLK"  LOC = "R9"  ; 
> NET "RAM_CSn"  LOC = "M3"  ; 
> NET "RAM_DQM<0>"  LOC = "L2"  ; 
> NET "RAM_DQM<1>"  LOC = "L3"  ; 
> NET "RAM_RASn"  LOC = "M2"  ; 
> NET "RAM_WEn"  LOC = "L5"  ; 
> NET "RESERVE_COLLECT"  LOC = "G3"  ; 
> NET "SYS_CLK_IN"  LOC = "T9"  ; 
> NET "SYS_CLK_OUT"  LOC = "R10"  ; 
> NET "SYS_Rst_IN"  LOC = "F5"  ; 
> 
> #PACE: Start of PACE Area Constraints
> 
> #PACE: Start of PACE Prohibit Constraints
> 
> #PACE: End of Constraints generated by PACE
> 
> --- Cheney Chen <email@hidden> skrev:
> 
> > Dear All.
> > 
> > I have meet a kernel boot error with my SZ030
> board
> > when using the kernel
> > compiled from  uClinux-dist-20051110-suzaku3.
> > The toolschain is microblaze-elf-tools-20060213.
> > 
> > The kernel can boot but stop at output "Freeing
> init
> > memory: 44K".
> > 
> > Dose someone have the same problem with me?
> > 
> > Please help me. :-)
> > Thank you very much
> > > _______________________________________________
> > suzaku-en mailing list
> > email@hidden
> >
>
http://lists.atmark-techno.com/mailman/listinfo/suzaku-en
> > 
> 
> 




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