[Suzaku-en:00603] Re: Configuring SZ410 with FPU

Muis, A. email@hidden
Thu May 22 15:45:25 JST 2008


Dear Mike,

I'm not this good in adaptation of the DCM but i will give it a try.
First check page 9 of the sz410-ja.pdf. On this page you can see the two
DCM's and their connection to the environment. You can see that the DDR
is running 1/2 the speed of the processorclock but the MPMC is just a
bit faster then the peripheral ddr bus. Next is the other peripheral bus
which is connected to the gpio,spi and rs232 and running at a 1/4 of the
processorclock. Same for the OCM TEMAC. Now my suggestion:

If you connect the second DCM directly to the oscillator you will get.

Processorclock 200MHz
Systemclock 100MHz
MPMC 200MHz
MPMC 90deg clock of 100MHz
MPMC 0deg clock of 100MHz

As I writing this I see some strange multiplication in DCM1 that
multiplies his input by 7. strange Another thing the systemclock of the
project is running at 1/4 of the processorclock

Andries

-----Original Message-----
From: email@hidden
[mailto:email@hidden] On Behalf Of Mike
Thompson
Sent: Tuesday, May 20, 2008 11:52 PM
To: SUZAKU general discussion list (in English)
Subject: [Suzaku-en:00602] Configuring SZ410 with FPU

I am attempting to configure a Suzaku SZ410 with a floating point unit. 
  To implement an FPU it appears the maximum speed I can run the 
processor clock (proc_clk_s) at is 233MHz and the system (bus) clock 
(sys_clk_s) must run at exactly 1/2 the frequency of the processor
clock.

By reviewing how the DCMs are configured (shown below) it appears the 
default Suzuku SZ410 ISE project MHS file configures the two DCMs to run

the processor clock at 350MHz and the system bus clock at 87.5 MHz.  Is 
my interpretation of this correct?

Can anyone suggest what changes I should make to these entires to meet 
the timing requirements to add an FPU to the virtex4 on the SZ410?  The 
changes I've attempted so far yield a non-running Suzaku.  I have a 
feeling I'm messing up the timing relationships between the PPC core, 
PLB bus and DDR SRAM and other unknown constraints between the various 
clock outputs of the DCMs.

Any help with this would be sincerely appreciated.

Mike Thompson

------------------------------------------
BEGIN dcm_module
  PARAMETER INSTANCE = dcm_ddr_fx
  PARAMETER HW_VER = 1.00.c
  PARAMETER C_CLK0_BUF = TRUE
  PARAMETER C_CLKFX_BUF = TRUE
  PARAMETER C_CLK2X_BUF = TRUE
  PARAMETER C_CLKFX_MULTIPLY = 7
  PARAMETER C_CLKFX_DIVIDE = 4
  PARAMETER C_CLKIN_PERIOD = 10.000
  PARAMETER C_CLK_FEEDBACK = 1X
  PARAMETER C_DFS_FREQUENCY_MODE = LOW
  PARAMETER C_DLL_FREQUENCY_MODE = LOW
  PARAMETER C_EXT_RESET_HIGH = 0
  PORT CLKIN = SYS_CLK_IN
  PORT CLKFB = dcm_ddr_fx_CLKFB
  PORT CLK0 = dcm_ddr_fx_CLKFB
  PORT CLK2X = clk_200mhz_s
  PORT CLKFX = clk_ddr
  PORT RST = net_vcc
  PORT LOCKED = dcm_ddr_fx_LOCKED
END

BEGIN dcm_module
  PARAMETER INSTANCE = dcm_ddr_clk
  PARAMETER HW_VER = 1.00.c
  PARAMETER C_CLK0_BUF = TRUE
  PARAMETER C_CLK90_BUF = TRUE
  PARAMETER C_CLK2X_BUF = TRUE
  PARAMETER C_CLKDV_BUF = TRUE
  PARAMETER C_DLL_FREQUENCY_MODE = HIGH
  PARAMETER C_CLKIN_PERIOD = 5.714285
  PARAMETER C_EXT_RESET_HIGH = 0
  PARAMETER C_CLKDV_DIVIDE = 2.0
  PORT CLKIN = clk_ddr
  PORT CLKFB = DDR_SDRAM_64Mx32_mpmc_clk_0_s
  PORT CLK0 = DDR_SDRAM_64Mx32_mpmc_clk_0_s
  PORT CLK90 = DDR_SDRAM_64Mx32_mpmc_clk_90_s
  PORT CLK2X = proc_clk_s
  PORT CLKDV = sys_clk_s
  PORT LOCKED = Dcm_all_locked
  PORT RST = dcm_ddr_fx_LOCKED
END
------------------------------------------

_______________________________________________
suzaku-en mailing list
email@hidden
http://lists.atmark-techno.com/mailman/listinfo/suzaku-en
###########################################

This message has been scanned by F-Secure Anti-Virus for Microsoft Exchange.
For more information, connect to http://www.f-secure.com/



More information about the suzaku-en mailing list