[Suzaku-en:00843] Re: Simulating mpmc_sz410_v2_01_a

mio email@hidden
Thu May 6 10:05:30 JST 2010


Hi.

> Hi Everybody !
>
> I am trying to build a displaycontroller for a small TFT using Suzaku 
> SZ410. I would like to read the screen-data from DDR2 Ram using either 
> PLB or directly a spare port from MPMC. While I am not sure which 
> alternative to pick (PLB would be easier is suppose, but performance 
> could be a problem), I still need to learn to use PLB Bus, so I just 
> go this direction for experimental purpose.
>
> To simulate my Design, I am using the Bus Functional Model to drive a 
> simplified design containing a XPS_GPIO and MPMC_SZ410_V2_01_A as well 
> as to DCMs for Clocking the PLB and MPMC. In addition I downloaded a 
> verilog model of the DDR2 parts used on the SZ410.
>
> Sadly, the MPMC_SZ410 does not respond to my BFM stimuli, whereas the 
> XPS_GPIO behaves as expected. The MPMC_SZ410 does not drive the DDR2 
> Connections and doesnot respond to PLB Transactions. Each Transaction 
> is terminated by a PLB Timeout signal.
>
>
> I know this is a complex problem, but I have following questions:
>
> .) What could I possibly do wrong ? (I am new to DDR2 Design, I don't 
> expect a detailed step-by-step instruction but general guidelines and 
> practices also I am willing to read :-)
>
> .) Did anyone succeed in using a uptodate MPMC Version with Suzaku ? 
> For example MPMC_V4_03_A ? (That is building MPMC from scratch)
>
> .) Has anyone a sample MHS File using DDR2 in a custom design (Not 
> directly based on the sample project from the documentation) ?
>
Please check following IP core and datasheet(p.13 - p.17).
This IP core use MPMC Version with SUZAKU.
http://suzaku.atmark-techno.com/files/downloads/suzaku-io-boards/av/fpga/xps_siv00_v1_00_c.zip

> Thanks a lot,
>
> Julian Grahsl
>
> Following my MHS File and Testbench.
>
> Here is my MHS File:
>
> ------------------
>
>  PARAMETER VERSION = 2.1.0
>
>  PORT SYS_CLK_IN = SYS_CLK_IN, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
>
>  PORT xps_gpio_0_GPIO_IO_O_pin = xps_gpio_0_GPIO_IO_O, DIR = O, VEC = 
> [0:31]
>
>  PORT DDR_CLK_OUT = DDR_CLK_OUT, DIR = O, VEC = [0:1]
>
>  PORT DDR_CLK_OUTn = DDR_CLK_OUTn, DIR = O, VEC = [0:1]
>
> PORT DDR_DM = DDR_DM, DIR = O, VEC = [0:3]
>
>  PORT DDR_DQ = DDR_DQ, DIR = IO, VEC = [0:31]
>
>  PORT DDR_DQS = DDR_DQS, DIR = IO, VEC = [0:3]
>
>  PORT DDR_DQSn = DDR_DQSn, DIR = IO, VEC = [0:3]
>
>  PORT DDR0_CKE = DDR_CKE, DIR = O, VEC = [0:0]
>
>  PORT DDR0_CSn = DDR_CSn, DIR = O, VEC = [0:0]
>
>  PORT DDR0_ODT = DDR_ODT, DIR = O, VEC = [0:0]
>
>  PORT DDR0_RASn = DDR_RASn, DIR = O
>
> PORT DDR0_CASn = DDR_CASn, DIR = O
>
> PORT DDR0_WEn = DDR_WEn, DIR = O
>
> PORT DDR0_Addr = DDR_Addr, DIR = O, VEC = [0:12]
>
> PORT DDR0_BankAddr = DDR_BankAddr, DIR = O, VEC = [0:1]
>
>  PORT DDR1_CKE = DDR_CKE_2, DIR = O, VEC = [0:0]
>
>  PORT DDR1_CSn = DDR_CSn_2, DIR = O, VEC = [0:0]
>
>  PORT DDR1_ODT = DDR_ODT_2, DIR = O, VEC = [0:0]
>
>  PORT DDR1_RASn = DDR_RASn_2, DIR = O
>
> PORT DDR1_CASn = DDR_CASn_2, DIR = O
>
> PORT DDR1_WEn = DDR_WEn_2, DIR = O
>
> PORT DDR1_Addr = DDR_Addr_2, DIR = O, VEC = [0:12]
>
> PORT DDR1_BankAddr = DDR_BankAddr_2, DIR = O, VEC = [0:1]
>
> BEGIN bfm_synch
>
>  PARAMETER INSTANCE = bfm_synch_0
>
>  PARAMETER HW_VER = 1.00.a
>
>  PARAMETER C_NUM_SYNCH = 2
>
>  PORT TO_SYNCH_IN = bfm_synch_0_TO_SYNCH_IN
>
>  PORT FROM_SYNCH_OUT = plbv46_master_bfm_0_SYNCH_OUT & 
> plbv46_monitor_bfm_0_SYNCH_OUT
>
> END
>
> BEGIN plbv46_master_bfm
>
>  PARAMETER INSTANCE = my_master
>
>  PARAMETER HW_VER = 1.00.a
>
>  PARAMETER PLB_MASTER_ADDR_LO_0 = 0xffff0000
>
>  PARAMETER PLB_MASTER_ADDR_HI_0 = 0xffffffff
>
>  BUS_INTERFACE MPLB = my_plb
>
>  PORT SYNCH_IN = bfm_synch_0_TO_SYNCH_IN
>
>  PORT SYNCH_OUT = plbv46_master_bfm_0_SYNCH_OUT
>
> END
>
> BEGIN plb_v46
>
>  PARAMETER INSTANCE = my_plb
>
>  PARAMETER HW_VER = 1.04.a
>
>  PARAMETER C_EXT_RESET_HIGH = 0
>
>  PORT PLB_Clk = clk_ddr
>
>  PORT SYS_Rst = sys_bus_reset
>
> END
>
> BEGIN plbv46_monitor_bfm
>
>  PARAMETER INSTANCE = my_monitor
>
>  PARAMETER HW_VER = 1.00.a
>
>  BUS_INTERFACE MON_PLB = my_plb
>
>  PORT SYNCH_IN = bfm_synch_0_TO_SYNCH_IN
>
>  PORT SYNCH_OUT = plbv46_monitor_bfm_0_SYNCH_OUT
>
> END
>
> BEGIN xps_gpio
>
>  PARAMETER INSTANCE = gpio
>
>  PARAMETER HW_VER = 2.00.a
>
>  PARAMETER C_BASEADDR = 0xffff0000
>
>  PARAMETER C_HIGHADDR = 0xffffffff
>
>  BUS_INTERFACE SPLB = my_plb
>
>  PORT GPIO_IO_O = xps_gpio_0_GPIO_IO_O
>
> END
>
> BEGIN dcm_module
>
>  PARAMETER INSTANCE = dcm_0
>
>  PARAMETER HW_VER = 1.00.d
>
>  PARAMETER C_CLK0_BUF = TRUE
>
>  PARAMETER C_CLKFX_BUF = TRUE
>
>  PARAMETER C_CLK2X_BUF = TRUE
>
>  PARAMETER C_CLKFX_MULTIPLY = 7
>
>  PARAMETER C_CLKFX_DIVIDE = 4
>
>  PARAMETER C_CLKIN_PERIOD = 10.000
>
>  PARAMETER C_CLK_FEEDBACK = 1X
>
>  PARAMETER C_DFS_FREQUENCY_MODE = LOW
>
>  PARAMETER C_DLL_FREQUENCY_MODE = LOW
>
>  PORT CLKIN = SYS_CLK_IN
>
>  PORT CLKFB = dcm_ddr_fx_CLKFB
>
>  PORT CLK0 = dcm_ddr_fx_CLKFB
>
>  PORT CLK2X = clk_200mhz_s
>
>  PORT CLKFX = clk_ddr
>
>  PORT RST = net_gnd
>
>  PORT LOCKED = dcm_ddr_fx_LOCKED
>
> END
>
> BEGIN dcm_module
>
>  PARAMETER INSTANCE = dcm_1
>
>  PARAMETER HW_VER = 1.00.d
>
>  PARAMETER C_CLK0_BUF = TRUE
>
>  PARAMETER C_CLK90_BUF = TRUE
>
>  PARAMETER C_CLK2X_BUF = TRUE
>
>  PARAMETER C_CLKDV_BUF = TRUE
>
>  PARAMETER C_DLL_FREQUENCY_MODE = HIGH
>
>  PARAMETER C_CLKIN_PERIOD = 5.714285
>
>  PARAMETER C_EXT_RESET_HIGH = 0
>
>  PARAMETER C_CLKDV_DIVIDE = 2.0
>
>  PORT CLKIN = clk_ddr
>
>  PORT CLKFB = DDR_SDRAM_64Mx32_mpmc_clk_0_s
>
>  PORT CLK0 = DDR_SDRAM_64Mx32_mpmc_clk_0_s
>
>  PORT CLK90 = DDR_SDRAM_64Mx32_mpmc_clk_90_s
>
>  PORT CLK2X = proc_clk_s
>
>  PORT CLKDV = sys_clk_s
>
>  PORT LOCKED = sys_bus_reset
>
>  PORT RST = dcm_ddr_fx_LOCKED
>
> END
>
> BEGIN mpmc_sz410
>
>  PARAMETER INSTANCE = mpmc_ddr2
>
>  PARAMETER HW_VER = 2.01.a
>
>  PARAMETER C_MEM_PARTNO = MT47H16M16-37E
>
>  PARAMETER C_MPMC_CLK0_PERIOD_PS = 5714
>
>  PARAMETER C_MPMC_BASEADDR = 0x00000000
>
>  PARAMETER C_MPMC_HIGHADDR = 0x03FFFFFF
>
>  PARAMETER C_MEM_DATA_WIDTH = 32
>
>  PARAMETER C_MEM_CLK_WIDTH = 2
>
>  PARAMETER C_SPLB0_P2P = 0
>
>  PARAMETER C_SPLB0_SUPPORT_BURSTS = 1
>
>  PARAMETER C_SPLB0_SMALLEST_MASTER = 64
>
>  BUS_INTERFACE SPLB0 = my_plb
>
>  PORT MPMC_Clk90 = DDR_SDRAM_64Mx32_mpmc_clk_90_s
>
>  PORT MPMC_Clk0 = DDR_SDRAM_64Mx32_mpmc_clk_0_s
>
>  PORT MPMC_Clk_200MHz = clk_200mhz_s
>
> PORT DDR2_DQS_n = DDR_DQSn
>
>  PORT DDR2_DQS = DDR_DQS
>
>  PORT DDR2_DM = DDR_DM
>
>  PORT DDR2_DQ = DDR_DQ
>
>  PORT DDR2_Addr = DDR_Addr
>
>  PORT DDR2_BankAddr = DDR_BankAddr
>
>  PORT DDR2_WE_n = DDR_WEn
>
> PORT DDR2_CAS_n = DDR_CASn
>
> PORT DDR2_RAS_n = DDR_RASn
>
>  PORT DDR2_ODT = DDR_ODT
>
>  PORT DDR2_CS_n = DDR_CSn
>
> PORT DDR2_CE = DDR_CKE
>
>  PORT DDR2_Addr_2 = DDR_Addr_2
>
> PORT DDR2_BankAddr_2 = DDR_BankAddr_2
>
> PORT DDR2_WE_n_2 = DDR_WEn_2
>
>  PORT DDR2_CAS_n_2 = DDR_CASn_2
>
> PORT DDR2_RAS_n_2 = DDR_RASn_2
>
>  PORT DDR2_ODT_2 = DDR_ODT_2
>
>  PORT DDR2_CS_n_2 = DDR_CSn_2
>
>  PORT DDR2_CE_2 = DDR_CKE_2
>
>  PORT DDR2_Clk_n = DDR_CLK_OUTn
>
> PORT DDR2_Clk = DDR_CLK_OUT
>
>  PORT MPMC_Rst = sys_bus_reset
>
> END
>
> And here my Testbench connecting DDR2 Models to Toplevel EDK design:
>
> library IEEE;
>
> use IEEE.STD_LOGIC_1164.ALL;
>
> library UNISIM;
>
> use UNISIM.VCOMPONENTS.ALL;
>
> -- START USER CODE (Do not remove this line)
>
> -- User: Put your libraries here. Code in this
>
> --       section will not be overwritten.
>
> -- END USER CODE (Do not remove this line)
>
> entity system_tb is
>
> end system_tb;
>
> architecture STRUCTURE of system_tb is
>
>   constant SYS_CLK_IN_PERIOD : time := 10000.000000 ps;
>
>   component ddr2 is
>
>     port (
>
>       ck : in std_logic;
>
>       ck_n : in  std_logic;
>
>       cke :  in  std_logic;
>
>       cs_n :  in  std_logic;
>
>       ras_n :  in  std_logic;
>
>       cas_n:  in  std_logic;
>
>       we_n:  in  std_logic;
>
>       dm_rdqs : inout std_logic_vector(1 downto 0);
>
>       ba  : inout std_logic_vector(1 downto 0);
>
>       addr :  inout std_logic_vector(12 downto 0);
>
>       dq : inout std_logic_vector(15 downto 0);
>
>       dqs : inout std_logic_vector(1 downto 0);
>
>       dqs_n : inout std_logic_vector(1 downto 0);
>
>       rdqs_n : out std_logic_vector(1 downto 0);
>
>       odt :  in  std_logic);
>
>   end component;
>
>   component system is
>
>     port (
>
>       SYS_CLK_IN : in std_logic;
>
>       xps_gpio_0_GPIO_IO_O_pin : out std_logic_vector(0 to 31);
>
>       DDR_CLK_OUT : out std_logic_vector(0 to 1);
>
>       DDR_CLK_OUTn : out std_logic_vector(0 to 1);
>
>       DDR_DM : out std_logic_vector(0 to 3);
>
>       DDR_DQ : inout std_logic_vector(0 to 31);
>
>       DDR_DQS : inout std_logic_vector(0 to 3);
>
>       DDR_DQSn : inout std_logic_vector(0 to 3);
>
>       DDR0_CKE : out std_logic_vector(0 to 0);
>
>       DDR0_CSn : out std_logic_vector(0 to 0);
>
>       DDR0_ODT : out std_logic_vector(0 to 0);
>
>       DDR0_RASn : out std_logic;
>
>       DDR0_CASn : out std_logic;
>
>       DDR0_WEn : out std_logic;
>
>       DDR0_Addr : out std_logic_vector(0 to 12);
>
>       DDR0_BankAddr : out std_logic_vector(0 to 1);
>
>       DDR1_CKE : out std_logic_vector(0 to 0);
>
>       DDR1_CSn : out std_logic_vector(0 to 0);
>
>       DDR1_ODT : out std_logic_vector(0 to 0);
>
>       DDR1_RASn : out std_logic;
>
>       DDR1_CASn : out std_logic;
>
>       DDR1_WEn : out std_logic;
>
>       DDR1_Addr : out std_logic_vector(0 to 12);
>
>       DDR1_BankAddr : out std_logic_vector(0 to 1)
>
>     );
>
>   end component;
>
>   -- Internal signals
>
>   signal DDR0_Addr : std_logic_vector(0 to 12);
>
>   signal DDR0_BankAddr : std_logic_vector(0 to 1);
>
>   signal DDR0_CASn : std_logic;
>
>   signal DDR0_CKE : std_logic_vector(0 to 0);
>
>   signal DDR0_CSn : std_logic_vector(0 to 0);
>
>   signal DDR0_ODT : std_logic_vector(0 to 0);
>
>   signal DDR0_RASn : std_logic;
>
>   signal DDR0_WEn : std_logic;
>
>   signal DDR1_Addr : std_logic_vector(0 to 12);
>
>   signal DDR1_BankAddr : std_logic_vector(0 to 1);
>
>   signal DDR1_CASn : std_logic;
>
>   signal DDR1_CKE : std_logic_vector(0 to 0);
>
>   signal DDR1_CSn : std_logic_vector(0 to 0);
>
>   signal DDR1_ODT : std_logic_vector(0 to 0);
>
>   signal DDR1_RASn : std_logic;
>
>   signal DDR1_WEn : std_logic;
>
>   signal DDR_CLK_OUT : std_logic_vector(0 to 1);
>
>   signal DDR_CLK_OUTn : std_logic_vector(0 to 1);
>
>   signal DDR_DM : std_logic_vector(0 to 3);
>
>   signal DDR_DQ : std_logic_vector(0 to 31);
>
>   signal DDR_DQS : std_logic_vector(0 to 3);
>
>   signal DDR_DQSn : std_logic_vector(0 to 3);
>
>   signal SYS_CLK_IN : std_logic;
>
>   signal xps_gpio_0_GPIO_IO_O_pin : std_logic_vector(0 to 31);
>
>   -- START USER CODE (Do not remove this line)
>
>   -- User: Put your signals here. Code in this
>
>   --       section will not be overwritten.
>
>   -- END USER CODE (Do not remove this line)
>
> begin
>
>   dut : system
>
>     port map (
>
>       SYS_CLK_IN => SYS_CLK_IN,
>
>       xps_gpio_0_GPIO_IO_O_pin => xps_gpio_0_GPIO_IO_O_pin,
>
>       DDR_CLK_OUT => DDR_CLK_OUT,
>
>       DDR_CLK_OUTn => DDR_CLK_OUTn,
>
> DDR_DM => DDR_DM,
>
>       DDR_DQ => DDR_DQ,
>
>       DDR_DQS => DDR_DQS,
>
>       DDR_DQSn => DDR_DQSn,
>
> DDR0_CKE => DDR0_CKE(0 to 0),
>
>       DDR0_CSn => DDR0_CSn(0 to 0),
>
> DDR0_ODT => DDR0_ODT(0 to 0),
>
>       DDR0_RASn => DDR0_RASn,
>
>       DDR0_CASn => DDR0_CASn,
>
>       DDR0_WEn => DDR0_WEn,
>
>       DDR0_Addr => DDR0_Addr,
>
>       DDR0_BankAddr => DDR0_BankAddr,
>
>       DDR1_CKE => DDR1_CKE(0 to 0),
>
> DDR1_CSn => DDR1_CSn(0 to 0),
>
> DDR1_ODT => DDR1_ODT(0 to 0),
>
>       DDR1_RASn => DDR1_RASn,
>
>       DDR1_CASn => DDR1_CASn,
>
>       DDR1_WEn => DDR1_WEn,
>
>       DDR1_Addr => DDR1_Addr,
>
>       DDR1_BankAddr => DDR1_BankAddr
>
>     );
>
>   ddr2_module_0: ddr2
>
> port map (
>
>       ck      => DDR_CLK_OUT(0),
>
>       ck_n    => DDR_CLK_OUTn(0),
>
>       cke     => DDR0_CKE(0),
>
>       cs_n    => DDR0_CSn(0),
>
>       ras_n   => DDR0_RASn,
>
>       cas_n   => DDR0_CASn,
>
>       we_n    => DDR0_WEn,
>
> dm_rdqs => DDR_DM(0 to 1),
>
> dq      => DDR_DQ(0 to 15),
>
>       dqs     => DDR_DQS(0 to 1),
>
>       dqs_n   => DDR_DQS(0 to 1),
>
>       ba      => DDR0_BankAddr,
>
>       addr    => DDR0_Addr,
>
> rdqs_n  => open,
>
>       odt     => DDR0_ODT(0));
>
>     ddr2_module_1: ddr2
>
>     port map (
>
> ck      => DDR_CLK_OUT(1),
>
>       ck_n    => DDR_CLK_OUTn(1),
>
>       cke     => DDR1_CKE(0),
>
>       cs_n    => DDR1_CSn(0),
>
>       ras_n   => DDR1_RASn,
>
> cas_n   => DDR1_CASn,
>
>       we_n    => DDR1_WEn,
>
> dm_rdqs => DDR_DM(2 to 3),
>
> dq      => DDR_DQ(16 to 31),
>
>       dqs     => DDR_DQS(2 to 3),
>
>       dqs_n   => DDR_DQS(2 to 3),
>
>       ba      => DDR1_BankAddr,
>
>       addr    => DDR1_Addr,
>
> rdqs_n  => open,
>
>       odt     => DDR0_ODT(0));
>
> -- Clock generator for SYS_CLK_IN
>
>   process
>
>   begin
>
>     SYS_CLK_IN <= '0';
>
>     loop
>
>       wait for (SYS_CLK_IN_PERIOD/2);
>
>       SYS_CLK_IN <= not SYS_CLK_IN;
>
>     end loop;
>
>   end process;
>
> end architecture STRUCTURE;
>
regards.

--
mio
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