[Suzaku:01638] Re: Dフリップフロップ

Keichi KAWAOKA email@hidden
2009年 8月 27日 (木) 19:30:49 JST


$email@hidden,$G$9!#(B

nSW1$B$,%0%m!<%P%k%/%m%C%/$K3d$j$"$?$C$F$$$J$$$N$+$b$7$l$^$;$s!#(B
$B2<5-$N$h$&$J46$8$G(BBUFG$B$H$$$&$b$N$r;H$C$F!"(B
$BG$0U$K3d$jEv$F$r$7$F$_$F$$$?$@$1$^$9$+!)(B

-><- $BNc(B -><-

COMPONENT BUFG
PORT (
	O : OUT STD_LOGIC;
	I : IN STD_LOGIC);
END COMPONENT;

$B!&!&!&(B
BUF_0 : BUFG
PORT MAP (
	I => nSW1,
	O => SYS_CLK
);




$B>e1r!!9d(B $B$5$s$O=q$-$^$7$?(B:
> $B>e1r$G$9!#(B
> $B$42sEz$"$j$,$H$&$4$6$$$^$9!#(B
> 
> $BAaB.$G$9$,!$(B
>> SUZAKU$B%9%?!<%?!<%-%C%H%,%$%I(B FPGA$BJT$N(B7.ISE $B$N;H$$J}$N>O$O(B
>> $B$&$^$/$$$-$^$9$G$7$g$&$+!#(B
> 
> $B>e5-$&$^$/F0$$$F$$$^$9!#(B
> 8.VHDL$B$K$h$k%m%8%C%/@_7W$G$N%\%?%sF~NO$b$&$^$/F0$$$F$$$^$9!#(B
> 
> $B<!$J$k$4;X<($rD:$1$k$H9,$$$G$9!#(B
> 
> 
> ----- Original Message ----- From: "Keichi KAWAOKA" 
> <email@hidden>
> To: "SUZAKU general discussion list" <email@hidden>
> Sent: Thursday, August 27, 2009 9:59 AM
> Subject: [Suzaku:01635] Re: $B#D%U%j%C%W%U%m%C%W(B
> 
> 
>> $email@hidden,$G$9!#(B
>>
>>> $B!V(BSUZAKU$B%9%?!<%?!<%-%C%H%,%$%I(B FPGA$BJT!W(B
>> $B!&!&!&!&(B
>>> $B$<$R!"$3$A$i$rDL$7;n$7$F$$$?$@$1$l$P$H;W$C$F$$$^$9!#(B
>> uezono$B$5$s$O$9$G$K$*;n$7$$$?$@$$$F$^$$$7$?$M!#!#!#$9$_$^$;$s!#(B
>> ($B2a5n$N%m%0$r3NG'$7$F$^$;$s$G$7$?!#(B)
>>
>>
>> $B$"$i$?$a$^$7$F!"!"!"(B
>>
>> SUZAKU$B%9%?!<%?!<%-%C%H%,%$%I(B FPGA$BJT$N(B7.ISE $B$N;H$$J}$N>O$O(B
>> $B$&$^$/$$$-$^$9$G$7$g$&$+!#(B
>> LED$B$r$D$1$?$j!"%9%$%C%A$rF~NO$7$?$j$G$-$k$+$I$&$+$r(B
>> $B$43NG'$r$$$?$@$1$l$P$H;W$C$F$$$^$9!#(B
>>
>>
>>
>> Keichi KAWAOKA $B$5$s$O=q$-$^$7$?(B:
>>> $email@hidden,$G$9!#(B
>>>
>>> $B$*$=$i$/!"(BIO$B%T%s$email@hidden$,$&$^$/$$$C$F$$$J$$$N$G$O$H9M$($i$l$^$9!#!#!#(B
>>>
>>>
>>> $B=i$a$F(BSUZAKU$B$r;H$o$l$kJ}$K!"(B
>>> $B!V(BSUZAKU$B%9%?!<%?!<%-%C%H%,%$%I(B FPGA$BJT!W(B
>>> http://suzaku.atmark-techno.com/files/downloads/suzaku-starter-kit/suzaku_starter_kit_guide_fpga_ja-2.4.6.pdf 
>>>
>>> $B$rMQ0U$7$F$*$j$^$9!#(B
>>> $B$<$R!"$3$A$i$rDL$7;n$7$F$$$?$@$1$l$P$H;W$C$F$$$^$9!#(B
>>>
>>>
>>> FPGA$B=i?4<T$NJ}$G$b!"$[$\BZ$j$J$/:G8e$^$G$?$I$j$D$1$k$H;W$o$l$^$9!#(B
>>> $B$^$?!":G8e$^$GDL$7$F$?$@$1$l$P(BSUZAKU$B$G$N3+H/$NN.$l$,$D$+$a$k$+$H;W$C(B 
>>> $B$F$$$^$9!#(B
>>>
>>>
>>> $B>e1r!!9d(B $B$5$s$O=q$-$^$7$?(B:
>>>> uezono$B$H?=$7$^$9!#!J(BFPGA$BNr!!0l%v7nL$K~!K(B
>>>>
>>>> $B#D%U%j%C%W%U%m%C%W!J$b$I$-!K$r(Bsuzakku$B>e$GF0$+$7$F$_$h$&$H;W$$!$(B
>>>> $B2<5-$N$h$&$K%W%m%0%i%`$7$^$7$?$i!$%(%i!<$K$J$j$^$7$?!#(B
>>>>
>>>> *)$B%/%m%C%/$H%j%;%C%H$NBe$o$j$K!$(BLED$B%\!<%I$N%\%?%s$K3d$jEv$F$i$l$??.9f$r(B
>>>> $BMQ$$$h$&$H$7$F$$$^$9!#(B
>>>>
>>>> $B-!$3$N$h$&$J;H$$J}$O$G$-$J$$$N$G$7$g$&$+!)(B
>>>> $B-";H$($k$H$7$?$i!$$I$N$h$&$KBP=h$9$l$P$h$m$7$$$G$7$g$&$+!#(B
>>>> $B!J%$%s%W%j%a%s%F!<%7%g%s(B $B%*%W%7%g%s$r;HMQ(B
>>>> $B!!(BXST
>>>> $B!!(B-keep_hierarchy No
>>>> $B!!(B-read_cores No
>>>> $B!!!!$H$"$k$N$G$9$,!&!&!&!K(B
>>>>
>>>> $B$465<x$$$?$@$1$k$H9,$$$G$9!#(B
>>>>
>>>> $B!]!]!]!]!]!]!]!]!]!]!]!]5-!]!]!]!]!]!]!]!]!]!]!]!]!]!](B
>>>>
>>>> $B%W%m%0%i%`!]!]!]!]!]!]!]!]!]!]!]!]!]!]!]!]!](B
>>>> entity top is
>>>> Port (
>>>> $B!!!!(BnLE0 : out STD_LOGIC;
>>>> $B!!!!(BnSW0 : in STD_LOGIC;
>>>> $B!!!!(BnSW1 : in STD_LOGIC
>>>> );
>>>> end top;
>>>>
>>>> --$B%"!<%-%F%/%A%c(B($B2sO)K\BN(B)
>>>> architecture IMP of top is
>>>> $B!!(Bbegin
>>>> $B!!(Bprocess(nSW1,nSW0)
>>>> $B!!(Bbegin
>>>>  $B!!!!(Bif nSW0='0' then
>>>>   $B!!!!!!!!(BnLE0 <= '0';
>>>>  $B!!!!(Belsif nSW1'event and nSW1='0' then
>>>>   $B!!!!!!!!(BnLE0 <= '1';
>>>>  $B!!!!(Bend if;
>>>> $B!!(Bend process;
>>>> end IMP;
>>>>
>>>> $B%(%i!<%a%C%;!<%8!]!]!]!]!]!]!]!]!]!]!]!]!]!]!]!]!](B
>>>> ERROR:Place:1018 - A clock IOB / clock component pair have been found
>>>> that are not placed at an optimal clock IOB /
>>>>
>>>> Started : "Generate Programming File".
>>>> ERROR:PhysDesignRules:10 - The network <nSW0_IBUF> is completely 
>>>> unrouted.
>>>> ERROR:PhysDesignRules:10 - The network <nSW1_BUFGP/IBUFG> is completely
>>>>   unrouted.
>>>> ERROR:PhysDesignRules:10 - The network <nSW1_BUFGP> is completely 
>>>> unrouted.
>>>> ERROR:PhysDesignRules:10 - The network <GLOBAL_LOGIC1> is completely
>>>> unrouted.
>>>> ERROR:Bitgen:25 - DRC detected 4 errors and 0 warnings.
>>>>
>>>>
>>>> $B!]!]!]!]!]!]!]!]!]!]!]!]!]!]!](B
>>>> $BEvJ}4D6-(B
>>>> $B!&(BISE Ver10.1$B!!(Bweb
>>>> $B!&(BSZ-130SIL
>>>> $B!JB>$KI,MW$J>pJs$,$"$j$^$7$?$i65$($F$/$@$5$$!K(B
>>>>
>>>>
>>>>
>>>> ------------------------------------------------------------------------ 
>>>>
>>>>
>>>> _______________________________________________
>>>> suzaku mailing list
>>>> email@hidden
>>>> http://lists.atmark-techno.com/cgi-bin/mailman/listinfo/suzaku
>>
> 
> 
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