[Suzaku:01366] ユーザIPコアの追加について

[菊地 義和]

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  ------------------------------------------
  -- Signals for user logic slave model s/w accessible register example
  ------------------------------------------
  signal slv_reg0                       : std_logic_vector(0 to 
C_SLV_DWIDTH-1);
  signal slv_reg1                       : std_logic_vector(0 to 
C_SLV_DWIDTH-1);
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  fdd_driver_0 : entity fdd_rdtrns_v1_00_a.fdd_driver--$B%i%$%V%i%j(B
   port map(
    SYS_CLK => Bus2IP_Clk  ,
    SYS_RST => Bus2IP_Reset ,
    -- External
    S_OUT => DATA1 ,
    --R/W CPU$B$+$i%"%/%;%9(B
    DATA_IN => slv_reg0(0 to 15),
    START => slv_reg1(0),
    STATUS => slv_reg2(0),          $B"+$3$N9T$,%(%i!<$H$J$k!#!!(B
--   nLED  => LED
    inter => inter
   );

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=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

ERROR:Xst:528 - Multi-source in Unit <user_logic> on signal <slv_reg2<0>>;
this signal is connected to multiple drivers.
Drivers are:
  Output signal of FDCE instance
<fdd_rdtrns_0/USER_LOGIC_I/fdd_driver_0/ByteTrns_0/STATUS_OUT>
  Output signal of FDRE instance <fdd_rdtrns_0/USER_LOGIC_I/slv_reg2_0>


Total REAL time to Xst completion: 21.00 secs
Total CPU time to Xst completion: 20.58 secs
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