[Suzaku:01367] Re: ユーザIPコアの追加について

2009年 1月 27日 (火) 15:51:08 JST

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> 
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> 
>>> $B%*%j%8%J%k(BIP$B$N:email@hidden$GG:$s$G$7$^$$$^$7$?!#(B
>>> $B$I$J$?$+$465<x$r$*4j$$$G$-$^$9$G$7$g$&$+!#(B
>>> $B$*4j$$$7$?$$E@$O#2E@$G$9!#(B
>>>
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>>>
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>>> $B!!$9$k$3$H$@$HM}2r$7$F$*$j$^$9!#(B
>>>
>> $BFC$KLdBj$J$5$=$&$G$9!#(B
>> $B@$$NCf$K?'!9$"$k(BIP$B%3%"$rGA$$$F$_$F$/$@$5$$!#(B
> 
> 
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> $B!|$465<x$r$*4j$$$7$?$$$3$H!#(B
> $B!!-!%f!<%6(BIP$B$r@\B3$9$k:]$NFbIt%l%8%9%?$H$N@\B3J}K!(B
> $B!!-"FbIt%l%8%9%?!V(Bslv_regX$B!W$N;HMQJ}K!(B
> 
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> 
> $B!|9T$$$?$$$3$H(B
> $B%f!<%6(BIP$B$r:email@hidden$9$k!#(B
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> 
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> 
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> $B-!(BIP$B$N%l%8%9%?$email@hidden$1$k$K$O(BXPS$B$,EG$-=P$9%9%1%k%H%s$N(B
> $B<!$N2U=j$N%l%8%9%?$r2<0L%b%8%e!<%k$K@\B3$7$^$9!#(B
>   ------------------------------------------
>   -- Signals for user logic slave model s/w accessible register example
>   ------------------------------------------
>   signal slv_reg0                       : std_logic_vector(0 to 
> C_SLV_DWIDTH-1);
>   signal slv_reg1                       : std_logic_vector(0 to 
> C_SLV_DWIDTH-1);
> $B!&!&!&!&!&!&!&(B
> ($B0J2<N,(B)
> 
> 
> $B-"@\B3$O%i%$%V%i%j8F$S=P$7!"%3%s%]!<%M%s%H8F$S=P$7$J$I$N(B
> $B%$%s%9%?%s%email@hidden@.$G<!$N$h$&$K5-=R$7$^$9!#(B
>  $B2<5-!V(Bport map$B!WFb!":8JU$O%i%$%V%i%j%b%8%e!<%k$NDj5AL>!"(B
> $B1&JU$O8F$S=P$7B&$NDj5AL>!"$H$7$F$$$^$9!#(B
> 
>   fdd_driver_0 : entity fdd_rdtrns_v1_00_a.fdd_driver--$B%i%$%V%i%j(B
>    port map(
>     SYS_CLK => Bus2IP_Clk  ,
>     SYS_RST => Bus2IP_Reset ,
>     -- External
>     S_OUT => DATA1 ,
>     --R/W CPU$B$+$i%"%/%;%9(B
>     DATA_IN => slv_reg0(0 to 15),
>     START => slv_reg1(0),
>     STATUS => slv_reg2(0),          $B"+$3$N9T$,%(%i!<$H$J$k!#!!(B
> --   nLED  => LED
>     inter => inter
>    );
> 
$B$3$3$^$G8+$k8B$j$G$OFC$K%(%i!<$N860x$O$J$5$=$&$G$9!#(B

> $B-#(BGenerate Netlist$B$N<B9T(B
> $B<B9T$7$^$9!#$9$k$H!">e5-9T$,860x$H$J$j%(%i!<$K$J$j$^$9!#(B
> 
> $B!|5/$-$F$$$kLdBj(B
> $B%U%!%$%k!V(Buser_logic.vhd$B!W$N2<0L%b%8%e!<%k8F$S=P$7It$G(B
> $B<!$N>l9g(B($B2<5--!;2>H(B)$B$K%(%i!<(B($B2<5--";2>H(B)$B$H$J$k!#(B
> 
> $B;2>H-!(B
> Architecture section$B$N(Bslv_regX($B$$$/$D$+$"$j$^$9(B)$B$r(B
> $B;HMQ$9$k:]!"(B 3$B$D0J>e$N%l%8%9%?$r;HMQ$9$k$H(B
> Generate Netlist$B$G%(%i!<$H$J$k$h$&$K;W$o$l$^$9!#(B
> $B;H$$J}$K2?$+8m$j$,$"$k$N$G$7$g$&$+(B
> 
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> $B$H%(%i!<$,H/@8$7$^$9!#(B
> 
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> $B;2>H-"(B
> $B!V(BC:\suzaku\sz130-mmu_mdm_002_ooo6\synthesis\fdd_rdtrns_0_wrapper_xst.srp$B!W(B
> $B$NFbMF(B
> 
> $B$3$3$+$i(B-------------------
> $B!JA0N,!K(B
> =========================================================================
> *                         Low Level Synthesis                           *
> =========================================================================
> 
> ERROR:Xst:528 - Multi-source in Unit <user_logic> on signal <slv_reg2<0>>;
> this signal is connected to multiple drivers.
> Drivers are:
>   Output signal of FDCE instance
> <fdd_rdtrns_0/USER_LOGIC_I/fdd_driver_0/ByteTrns_0/STATUS_OUT>
>   Output signal of FDRE instance <fdd_rdtrns_0/USER_LOGIC_I/slv_reg2_0>
> 
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http://japan.xilinx.com/support/answers/14264.htm

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slv_reg2<0>$B$H(Bslv_reg2_0$B$,$*$+$7$J@\B3$K$J$C$F$$$J$$$+!"(B
$B8+D>$7$F$_$F$/$@$5$$!#(B

> 
> Total REAL time to Xst completion: 21.00 secs
> Total CPU time to Xst completion: 20.58 secs
> $B!J8eN,!K(B
> $B$3$3$^$G(B-----------------------
> 
> $B$h$m$7$/$*4j$$$$$?$7$^$9!#(B
> 
> $B0J>e(B 
>