[Suzaku:01368] Re: ユーザIPコアの追加について
菊地 義和
email@hidden
2009年 1月 27日 (火) 16:22:05 JST
$B5FCO$G$9!#(B
$B$*JV;v$"$j$,$H$&$4$6$$$^$9!#(B
> $B$b$7$+$9$k$H%=%j%e!<%7%g%s(B3$B$N8=>]$,$*$3$C$F$k$+$b!)(B
> slv_reg2<0>$B$H(Bslv_reg2_0$B$,$*$+$7$J@\B3$K$J$C$F$$$J$$$+!"(B
> $B8+D>$7$F$_$F$/$@$5$$!#(B
$B$9$_$^$;$s!#(B
$B$I$NJU$j$r8+$k$H$h$$$N$G$7$g$&$+!#(B
$B;d$O<!$NE@$r3NG'$7$^$7$?!#(B
$B!&:email@hidden$7$?(BVHDL$B$N%U%!%$%k$OA4$F(B
$B!&%U%!%$%k!V(Bfdd_rdtrns_0_wrapper_xst.srp$B!W$NFbMF(B
$B$=$l$G!"(Bslv_reg2<0>$B$H(Bslv_reg2_0$B$,$*$+$7$J@\B3C4$C$F$$$J$$$3$H$r(B
$B3NG'$7$?$D$b$j$G$*$j$^$9!#(B
$BB>$K!"3NG'%]%$%s%H$"$l$P$4;XE&$r$*4j$$$7$^$9!#(B
>> ERROR:Xst:528 - Multi-source in Unit <user_logic> on signal
>> <slv_reg2<0>>;
>> this signal is connected to multiple drivers.
>> Drivers are:
>> Output signal of FDCE instance
>> <fdd_rdtrns_0/USER_LOGIC_I/fdd_driver_0/ByteTrns_0/STATUS_OUT>
>> Output signal of FDRE instance <fdd_rdtrns_0/USER_LOGIC_I/slv_reg2_0>
$B>e5-%(%i!<>pJs$+$i<!$N$h$&$KBP1~$7$^$7$?!#(B
$B:email@hidden$7$?(BVHDL$B$N$J$+$G$O(B <slv_reg2<0>$B$NA`:n$O$7$F$^$9$,!"(B
STATUS_OUT$B$NA`:n$O$7$F$^$;$s!#(B
$B$^$?!";d$,Dj5A$7$?C<;R$OL$@\B3$N=PNO$,$J$/$J$k$h$&$K$b$7$^$7$?!#(B
$B$G$9$,!"%&%#%6!<%I$,EG$-=P$9%3!<%I$O=$@5$7$F$$$J$$$N$G!"(B
$B<!$N2U=j$O$=$N$^$^$H$J$j$^$9!#(B
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_reg0 : std_logic_vector(0 to
C_SLV_DWIDTH-1);
signal slv_reg1 : std_logic_vector(0 to
C_SLV_DWIDTH-1);
signal slv_reg2 : std_logic_vector(0 to
C_SLV_DWIDTH-1);
signal slv_reg3 : std_logic_vector(0 to
C_SLV_DWIDTH-1);
signal slv_reg4 : std_logic_vector(0 to
C_SLV_DWIDTH-1);
signal slv_reg5 : std_logic_vector(0 to
C_SLV_DWIDTH-1);
$B$=$&$9$k$H!"<!$N$h$&$J%(%i!<$email@hidden$8$^$9!#(B
Output signal of FDRE instance <fdd_rdtrns_0/USER_LOGIC_I/slv_reg0_13>
Output signal of FDRE instance <fdd_rdtrns_0/USER_LOGIC_I/slv_reg2_0>
$B$3$l$G!"2r7h$N%R%s%H$K$J$j$^$9$G$7$g$&$+!#(B
$B$h$m$7$/$*4j$$$7$^$9!#(B
$B0J>e(B
----- Original Message -----
From: "mio" <email@hidden>
To: "SUZAKU general discussion list" <email@hidden>
Sent: Tuesday, January 27, 2009 3:51 PM
Subject: [Suzaku:01367] Re: $B%f!<%6(BIP$B%3%"$NDI2C$K$D$$$F(B
> $BCfEg$G$9!#(B
>
> $B5FCO(B $B5AOB(B $B$5$s$O=q$-$^$7$?(B:
>> $B5FCO$H?=$7$^$9!#(B
>> $B$$$D$b;29M$K$5$;$F$$$?$@$$$F$*$j$^$9!#(B
>>
>>> $BCfEgMM(B
>> $BA02s!"%"%I%P%$%9$$$?$@$-!"$"$j$,$H$&$4$6$$$^$9!#(B
>> $B2?$H$+?J$s$G$*$j$^$9!#(B
>>
>>>> $B%*%j%8%J%k(BIP$B$N:email@hidden$GG:$s$G$7$^$$$^$7$?!#(B
>>>> $B$I$J$?$+$465<x$r$*4j$$$G$-$^$9$G$7$g$&$+!#(B
>>>> $B$*4j$$$7$?$$E@$O#2E@$G$9!#(B
>>>>
>>>> $B#1!%%*%j%8%J%k(BIP$B$NF~=PNO%l%8%9%?(B
>>>> $B!!!!%"%I%l%9!"5!G=$N7hDjJ}K!$O<!$N$h$&$J(B
>>>> $B!!!!M}2r$G$h$$$N$G$7$g$&$+!#(B
>>>>
>>>> $B!!%&%#%6!<%I$NCf$G%l%8%9%??t$email@hidden@$7$F$*$j$^$9(B
>>>> $B!!$,!"$3$N?t$O%*%j%8%J%k(BIP$B$KI,MQ$J%l%8%9%??t$H(B
>>>> $B!!$J$j$^$9!#$3$l$H!"(BIP$B$NF~=PNO$r$I$N$h$&$K@\B3(B
>>>> $B!!$9$k$+$,!"%*%j%8%J%k(BIP$B$N%l%8%9%?$N5!G=$r7hDj(B
>>>> $B!!$9$k$3$H$@$HM}2r$7$F$*$j$^$9!#(B
>>>>
>>> $BFC$KLdBj$J$5$=$&$G$9!#(B
>>> $B@$$NCf$K?'!9$"$k(BIP$B%3%"$rGA$$$F$_$F$/$@$5$$!#(B
>>
>>
>> $B$=$l$G!"EvJ}$N(BIP$B%3%"$r8+D>$7$?$H$3$m$$$/$D$+0-$$E@$,(B
>> $B8+$D$+$j!"=$@5$7$F$*$j$^$9!#(B
>>
>> $B$G$9$,!"$I$&$7$F$b2r7h$G$-$:!"$b$&>/$7$465<x$r(B
>> $B$*4j$$$G$-$J$$$G$7$g$&$+!#(B
>> $B"(D9J8$K$J$j!"?=$7Lu$"$j$^$;$s!#(B
>>
>> $B!|$465<x$r$*4j$$$7$?$$$3$H!#(B
>> $B!!-!%f!<%6(BIP$B$r@\B3$9$k:]$NFbIt%l%8%9%?$H$N@\B3J}K!(B
>> $B!!-"FbIt%l%8%9%?!V(Bslv_regX$B!W$N;HMQJ}K!(B
>>
>> $BEvJ}$NM}2r$r0J2<$K=q$-$^$7$?!#(B
>>
>> $B!|9T$$$?$$$3$H(B
>> $B%f!<%6(BIP$B$r:email@hidden$9$k!#(B
>> XPS$B$,EG$-=P$7$?%9%1%k%H%s$K(BISE$B$G:email@hidden$7$?(BVHDL$B%3!<%I$r(B
>> $BDI2C$7!"%f!<%6(BIP$B$r@\B3$7$?$$!#(B
>>
>> $B$=$N:]!"(BIP$B$r(BCPU$B$+$i@)8f$9$k$?$a$K!"$$$/$D$+$N%l%8%9%?$email@hidden$1$?$$!#(B
>>
>> $B!|EvJ}$NM}2r$H<B;\$7$?$3$H(B
>> $B-!(BIP$B$N%l%8%9%?$email@hidden$1$k$K$O(BXPS$B$,EG$-=P$9%9%1%k%H%s$N(B
>> $B<!$N2U=j$N%l%8%9%?$r2<0L%b%8%e!<%k$K@\B3$7$^$9!#(B
>> ------------------------------------------
>> -- Signals for user logic slave model s/w accessible register example
>> ------------------------------------------
>> signal slv_reg0 : std_logic_vector(0 to
>> C_SLV_DWIDTH-1);
>> signal slv_reg1 : std_logic_vector(0 to
>> C_SLV_DWIDTH-1);
>> $B!&!&!&!&!&!&!&(B
>> ($B0J2<N,(B)
>>
>>
>> $B-"@\B3$O%i%$%V%i%j8F$S=P$7!"%3%s%]!<%M%s%H8F$S=P$7$J$I$N(B
>> $B%$%s%9%?%s%email@hidden@.$G<!$N$h$&$K5-=R$7$^$9!#(B
>> $B2<5-!V(Bport map$B!WFb!":8JU$O%i%$%V%i%j%b%8%e!<%k$NDj5AL>!"(B
>> $B1&JU$O8F$S=P$7B&$NDj5AL>!"$H$7$F$$$^$9!#(B
>>
>> fdd_driver_0 : entity fdd_rdtrns_v1_00_a.fdd_driver--$B%i%$%V%i%j(B
>> port map(
>> SYS_CLK => Bus2IP_Clk ,
>> SYS_RST => Bus2IP_Reset ,
>> -- External
>> S_OUT => DATA1 ,
>> --R/W CPU$B$+$i%"%/%;%9(B
>> DATA_IN => slv_reg0(0 to 15),
>> START => slv_reg1(0),
>> STATUS => slv_reg2(0), $B"+$3$N9T$,%(%i!<$H$J$k!#!!(B
>> -- nLED => LED
>> inter => inter
>> );
>>
> $B$3$3$^$G8+$k8B$j$G$OFC$K%(%i!<$N860x$O$J$5$=$&$G$9!#(B
>
>> $B-#(BGenerate Netlist$B$N<B9T(B
>> $B<B9T$7$^$9!#$9$k$H!">e5-9T$,860x$H$J$j%(%i!<$K$J$j$^$9!#(B
>>
>> $B!|5/$-$F$$$kLdBj(B
>> $B%U%!%$%k!V(Buser_logic.vhd$B!W$N2<0L%b%8%e!<%k8F$S=P$7It$G(B
>> $B<!$N>l9g(B($B2<5--!;2>H(B)$B$K%(%i!<(B($B2<5--";2>H(B)$B$H$J$k!#(B
>>
>> $B;2>H-!(B
>> Architecture section$B$N(Bslv_regX($B$$$/$D$+$"$j$^$9(B)$B$r(B
>> $B;HMQ$9$k:]!"(B 3$B$D0J>e$N%l%8%9%?$r;HMQ$9$k$H(B
>> Generate Netlist$B$G%(%i!<$H$J$k$h$&$K;W$o$l$^$9!#(B
>> $B;H$$J}$K2?$+8m$j$,$"$k$N$G$7$g$&$+(B
>>
>> 3$B$D0J>e$N%l%8%9%?;HMQ$G%(%i!<H/@8$H;W$o$l$kM}M3(B
>> $B%(%i!<%3!<%I$rMj$j$K!"2<0L%b%8%e!<%k$r%3%a%s%H2=$7!"(B
>> $BD4::$7$^$7$?!#(B
>> $B$=$N7k2L!""+$G<($7$F$$$k9T$K!V(Bslv_regX$B!W$r;HMQ$9$k$H(B
>> $B$H%(%i!<$,H/@8$7$^$9!#(B
>>
> 3$B$D0J>e$@$+$i$H$$$C$F!"%(%i!<$,=P$k$3$H$O$J$$$H;W$&$N$G$9$,!&!&!&!#(B
>
>> $B;2>H-"(B
>>
>> $B!V(BC:\suzaku\sz130-mmu_mdm_002_ooo6\synthesis\fdd_rdtrns_0_wrapper_xst.srp$B!W(B>> $B$NFbMF(B>>>> $B$3$3$+$i(B------------------->> $B!JA0N,!K(B>> =========================================================================>> * Low Level Synthesis *>> =========================================================================>>>> ERROR:Xst:528 - Multi-source in Unit <user_logic> on signal<slv_reg2<0>>;>> this signal is connected to multiple drivers.>> Drivers are:>> Output signal of FDCE instance>> <fdd_rdtrns_0/USER_LOGIC_I/fdd_driver_0/ByteTrns_0/STATUS_OUT>>> Output signal of FDRE instance <fdd_rdtrns_0/USER_LOGIC_I/slv_reg2_0>>>> $B%(%i!<%a%C%;!<%8$h$j(BXilinx$B$N%5%$%H$G8!:w$7$F$_$^$7$?!#(B>> http://japan.xilinx.com/support/answers/14264.htm>> $B$b$7$+$9$k$H%=%j%e!<%7%g%s(B3$B$N8=>]$,$*$3$C$F$k$+$b!)(B> slv_reg2<0>$B$H(Bslv_reg2_0$B$,$*$+$7$J@\B3$K$J$C$F$$$J$$$+!"(B> $B8+D>$7$F$_$F$/$@$5$$!#(
B>>>>> Total REAL time to Xst completion: 21.00 secs>> Total CPU time to Xst completion: 20.58 secs>> $B!J8eN,!K(B>> $B$3$3$^$G(B----------------------->>>> $B$h$m$7$/$*4j$$$$$?$7$^$9!#(B>>>> $B0J>e(B>>>--------------------------------------------------------------------------------> _______________________________________________> suzaku mailing list> email@hidden> http://lists.atmark-techno.com/cgi-bin/mailman/listinfo/suzaku>
suzaku メーリングリストの案内